Add support for creating a auxiliary domain from the IOMMU device to implement per-instance pagetables. Also add a helper function to return the pagetable base address (ttbr) and asid to the caller so that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse jcrouse@codeaurora.org ---
drivers/gpu/drm/msm/msm_iommu.c | 97 +++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_mmu.h | 4 ++ 2 files changed, 101 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 1926329..adf9f18 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -21,9 +21,21 @@ struct msm_iommu { struct msm_mmu base; struct iommu_domain *domain; + u64 ttbr; + u32 asid; }; #define to_msm_iommu(x) container_of(x, struct msm_iommu, base)
+/* + * The asid is currently unused for arm-smmu-v2 since all the pagetable + * switching does a TLBIALL but still assign a somewhat unique number per + * instance to leave open the possibility of being smarter about it + * + * Accepted range is 32 to 255 (starting at 32 gives a cushion for the asids + * assigned to the real context banks in the arm-smmu driver. + */ +static int msm_iommu_asid = 32; + static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg) { @@ -34,6 +46,47 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, return 0; }
+static int msm_iommu_aux_attach(struct msm_mmu *mmu, const char * const *names, + int cnt) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + int ret; + + /* Attach the aux device */ + ret = iommu_aux_attach_device(iommu->domain, mmu->dev); + if (ret) + return ret; + + /* Get the base address of the pagetable */ + ret = iommu_domain_get_attr(iommu->domain, DOMAIN_ATTR_PTBASE, + &iommu->ttbr); + if (ret) + return ret; + + /* + * Assign an asid for the instance even though the code doesn't + * currently support per-asid TLB invalidation. There isn't any + * protection on this so two instances could in theory end up with the + * same ASID but that would have very minor performance implications if + * per-ASID TLB invalidation were to be enabled in the future + */ + iommu->asid = msm_iommu_asid++; + + if (msm_iommu_asid > 0xff) + msm_iommu_asid = 32; + + return 0; +} + +static void msm_iommu_aux_detach(struct msm_mmu *mmu, const char * const *names, + int cnt) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + + iommu->ttbr = 0; + iommu->asid = 0; +} + static int msm_iommu_attach(struct msm_mmu *mmu, const char * const *names, int cnt) { @@ -86,6 +139,50 @@ static const struct msm_mmu_funcs funcs = { .destroy = msm_iommu_destroy, };
+static const struct msm_mmu_funcs aux_funcs = { + .attach = msm_iommu_aux_attach, + .detach = msm_iommu_aux_detach, + .map = msm_iommu_map, + .unmap = msm_iommu_unmap, + .destroy = msm_iommu_destroy, +}; + +bool msm_iommu_get_ptinfo(struct msm_mmu *mmu, u64 *ttbr, u32 *asid) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + + if (!iommu->ttbr) + return false; + + if (ttbr) + *ttbr = iommu->ttbr; + if (asid) + *asid = iommu->asid; + + return true; +} + + +struct msm_mmu *msm_iommu_new_instance(struct device *dev) +{ + struct msm_iommu *iommu; + + iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); + if (!iommu) + return ERR_PTR(-ENOMEM); + + /* Create a new domain that will be attached as an aux domain */ + iommu->domain = iommu_domain_alloc(&platform_bus_type); + if (!iommu->domain) { + kfree(iommu); + return ERR_PTR(-ENOMEM); + } + + msm_mmu_init(&iommu->base, dev, &aux_funcs); + + return &iommu->base; +} + struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) { struct msm_iommu *iommu; diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index d21b266..f430903 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -46,6 +46,10 @@ static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev, struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu);
+struct msm_mmu *msm_iommu_new_instance(struct device *dev); + +bool msm_iommu_get_ptinfo(struct msm_mmu *mmu, u64 *ttbr, u32 *asid); + static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, int (*handler)(void *arg, unsigned long iova, int flags)) {