[Bug 48880] Set mode has different timings than requested on VGA

https://bugs.freedesktop.org/show_bug.cgi?id=48880

--- Comment #24 from Alex Deucher agd5f@yahoo.com 2012-04-19 08:20:03 PDT --- (In reply to comment #23)

The trick is testing a given version of the chip to the death and finding the frequency limits of the inner loop of the pll. I have always managed to fully clamp down pll ranges with a halfway decent CRT. It does take time and a structured approach though.

Even then you still hit problematic monitors. CRTs are usually pretty forgiving; it's usually digital monitors that have problems.