Add cmdq support for mtk-mmsys config API. The mmsys config register settings need to take effect with the other HW settings(like OVL_ADAPTOR...) at the same vblanking time.
If we use CPU to write the mmsys reg, we can't guarantee all the settings can be written in the same vblanking time. Cmdq is used for this purpose. We prepare all the related HW settings in one cmdq packet. The first command in the packet is "wait stream done", and then following with all the HW settings. After the cmdq packet is flush to GCE HW. The GCE waits for the "stream done event" to coming and then starts flushing all the HW settings. This can guarantee all the settings flush in the same vblanking.
Signed-off-by: Nancy.Lin nancy.lin@mediatek.com --- drivers/soc/mediatek/mtk-mmsys.c | 29 ++++++++++++++++++++------ include/linux/soc/mediatek/mtk-mmsys.h | 6 +++++- 2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 545a9cee8b7b..868df83eb57d 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -88,6 +88,7 @@ struct mtk_mmsys { const struct mtk_mmsys_driver_data *data; spinlock_t lock; /* protects mmsys_sw_rst_b reg */ struct reset_controller_dev rcdev; + struct cmdq_client_reg cmdq_base; };
void mtk_mmsys_ddp_connect(struct device *dev, @@ -180,7 +181,7 @@ static const struct reset_control_ops mtk_mmsys_reset_ops = { };
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, - u32 id, u32 val) + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt) { struct mtk_mmsys *mmsys = dev_get_drvdata(dev); const struct mtk_mmsys_config *mmsys_config = mmsys->data->config; @@ -188,7 +189,6 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, u32 mask; u32 offset; int i; - u32 tmp;
if (!mmsys->data->num_configs) return; @@ -204,10 +204,20 @@ void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, mask = mmsys_config[i].mask; reg_val = val << mmsys_config[i].shift;
- tmp = readl(mmsys->regs + offset); - - tmp = (tmp & ~mask) | reg_val; - writel(tmp, mmsys->regs + offset); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (cmdq_pkt && mmsys->cmdq_base.size) { + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys, + mmsys->cmdq_base.offset + offset, reg_val, + mask); + } else { +#endif + u32 tmp = readl(mmsys->regs + offset); + + tmp = (tmp & ~mask) | reg_val; + writel(tmp, mmsys->regs + offset); +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + } +#endif } EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_config);
@@ -243,6 +253,13 @@ static int mtk_mmsys_probe(struct platform_device *pdev) }
mmsys->data = of_device_get_match_data(&pdev->dev); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0); + if (ret) + dev_dbg(dev, "No mediatek,gce-client-reg!\n"); +#endif + platform_set_drvdata(pdev, mmsys);
clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index b2d2310d7e7a..3e998bfb795a 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -6,6 +6,10 @@ #ifndef __MTK_MMSYS_H #define __MTK_MMSYS_H
+#include <linux/mailbox_controller.h> +#include <linux/mailbox/mtk-cmdq-mailbox.h> +#include <linux/soc/mediatek/mtk-cmdq.h> + enum mtk_ddp_comp_id; struct device;
@@ -78,6 +82,6 @@ void mtk_mmsys_ddp_disconnect(struct device *dev, enum mtk_ddp_comp_id next);
void mtk_mmsys_ddp_config(struct device *dev, enum mtk_mmsys_config_type config, - u32 id, u32 val); + u32 id, u32 val, struct cmdq_pkt *cmdq_pkt);
#endif /* __MTK_MMSYS_H */