On Thu, 2017-07-27 at 15:47 +0300, Andrey Gusakov wrote:
Minimum pixel clock period is 6.5 nS for DPI. Do not accept modes with lower pixel clock period.
Signed-off-by: Andrey Gusakov andrey.gusakov@cogentembedded.com
drivers/gpu/drm/bridge/tc358767.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index f605bb7d1aa3..e8008e0c2e88 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -1103,7 +1103,10 @@ static bool tc_bridge_mode_fixup(struct drm_bridge *bridge, static int tc_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) {
- /* Accept any mode */
- /* PCLK limitation = 6.5 nS */
- if (mode->clock > 163000)
return MODE_CLOCK_HIGH;
The comment doesn't match the code. If the limit is 6.5 nS, shouldn't that be if (mode->clock > 153846) ?
regards Philipp