On Wed, 09 Dec 2020, Lyude Paul lyude@redhat.com wrote:
Noticed this while moving all of the VESA backlight code in i915 over to DRM helpers: it would appear that we calculate the frequency value we want to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never actually changes during runtime. So, let's simplify things by just caching this value in intel_panel.backlight, and re-writing it as-needed.
This isn't a full review, just something I spotted so far. Please see inline.
BR, Jani.
Signed-off-by: Lyude Paul lyude@redhat.com Cc: Jani Nikula jani.nikula@intel.com Cc: Dave Airlie airlied@gmail.com Cc: greg.depoire@gmail.com
.../drm/i915/display/intel_display_types.h | 1 + .../drm/i915/display/intel_dp_aux_backlight.c | 64 ++++++------------- 2 files changed, 19 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 5bc5bfbc4551..133c9cb742a7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -259,6 +259,7 @@ struct intel_panel {
/* DPCD backlight */ u8 pwmgen_bit_count;
u8 pwm_freq_pre_divider;struct backlight_device *device;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 4fd536801b14..94ce5ca1affa 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -129,50 +129,6 @@ intel_dp_aux_set_backlight(const struct drm_connector_state *conn_state, u32 lev } }
-/*
- Set PWM Frequency divider to match desired frequency in vbt.
- The PWM Frequency is calculated as 27Mhz / (F x P).
- Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
- Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)- */
-static bool intel_dp_aux_set_pwm_freq(struct intel_connector *connector) -{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- const u8 pn = connector->panel.backlight.pwmgen_bit_count;
- int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
- freq = dev_priv->vbt.backlight.pwm_freq_hz;
- if (!freq) {
drm_dbg_kms(&dev_priv->drm,"Use panel default backlight frequency\n");return false;- }
- fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
- f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
- fxp_actual = f << pn;
- /* Ensure frequency is within 25% of desired value */
- fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
- fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
- if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");return false;- }
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {drm_dbg_kms(&dev_priv->drm,"Failed to write aux backlight freq\n");return false;- }
- return true;
-}
static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { @@ -213,9 +169,13 @@ static void intel_dp_aux_enable_backlight(const struct intel_crtc_state *crtc_st break; }
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
if (intel_dp_aux_set_pwm_freq(connector))
if (panel->backlight.pwm_freq_pre_divider) {
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,panel->backlight.pwm_freq_pre_divider) == 1) new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;elsedrm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");}
if (new_dpcd_buf != dpcd_buf) { if (drm_dp_dpcd_writeb(&intel_dp->aux,
@@ -236,6 +196,14 @@ static void intel_dp_aux_disable_backlight(const struct drm_connector_state *old false); }
+/*
- Compute PWM frequency divider value based off the frequency provided to us by the vbt.
- The PWM Frequency is calculated as 27Mhz / (F x P).
- Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
- Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)- */
static u32 intel_dp_aux_calc_max_backlight(struct intel_connector *connector) { struct drm_i915_private *i915 = to_i915(connector->base.dev); @@ -287,8 +255,10 @@ static u32 intel_dp_aux_calc_max_backlight(struct intel_connector *connector) pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- /* Ensure frequency is within 25% of desired value */ fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
- if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { drm_dbg_kms(&i915->drm, "VBT defined backlight frequency out of range\n");
@@ -309,7 +279,9 @@ static u32 intel_dp_aux_calc_max_backlight(struct intel_connector *connector) "Failed to write aux pwmgen bit count\n"); return max_backlight; }
- panel->backlight.pwmgen_bit_count = pn;
- panel->backlight.pwm_freq_pre_divider = f;
This should be wrapped in
if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
but you do it in the next patch, so this patch is a bit broken.
max_backlight = (1 << pn) - 1;