[PATCH v1 16/26] drm/msm/dsi: limit vco_delay to 28nm PHY

Only 28nm PHY requires sleeping during the VCO rate setting procedure. Rewrite sleeping for 28nm and drop vco_delay from the rest of PHYs.

Signed-off-by: Dmitry Baryshkov dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c | 3 --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 4 ---- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 10 ++++------ drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 3 --- 4 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c index 81ca0cf2a3ad..7533db8955a5 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c @@ -96,7 +96,6 @@ struct dsi_pll_10nm { /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock;

- int vco_delay; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup;

@@ -768,8 +767,6 @@ static int dsi_pll_10nm_init(struct msm_dsi_phy *phy) pll = &pll_10nm->base; pll->cfg = phy->cfg;

- pll_10nm->vco_delay = 1; - ret = pll_10nm_register(pll_10nm, phy->provided_clocks); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index c531ddf26521..023727623847 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -122,8 +122,6 @@ struct dsi_pll_14nm { void __iomem *phy_cmn_mmio; void __iomem *mmio;

- int vco_delay; - struct dsi_pll_input in; struct dsi_pll_output out;

@@ -1012,8 +1010,6 @@ static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) pll = &pll_14nm->base; pll->cfg = phy->cfg;

- pll_14nm->vco_delay = 1; - ret = pll_14nm_register(pll_14nm, phy->provided_clocks); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index fa96bfc21fdb..e77b21f0d3bf 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -69,8 +69,6 @@ struct dsi_pll_28nm { struct platform_device *pdev; void __iomem *mmio;

- int vco_delay; - struct pll_28nm_cached_state cached_state; };

@@ -209,8 +207,10 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, pll_write(base + REG_DSI_28nm_PHY_PLL_SDM_CFG4, 0x00);

/* Add hardware recommended delay for correct PLL configuration */ - if (pll_28nm->vco_delay) - udelay(pll_28nm->vco_delay); + if (pll->cfg->type == MSM_DSI_PHY_28NM_HPM) + udelay(1); + else /* LP */ + udelay(1000);

pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg); pll_write(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00); @@ -576,7 +576,6 @@ static int dsi_pll_28nm_hpm_init(struct msm_dsi_phy *phy) }

pll = &pll_28nm->base; - pll_28nm->vco_delay = 1;

pll->cfg = phy->cfg;

@@ -616,7 +615,6 @@ static int dsi_pll_28nm_lp_init(struct msm_dsi_phy *phy) }

pll = &pll_28nm->base; - pll_28nm->vco_delay = 1000;

pll->cfg = phy->cfg;

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index c6f0aca66fa9..d3fea4a2b498 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -96,7 +96,6 @@ struct dsi_pll_7nm { /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock;

- int vco_delay; struct dsi_pll_config pll_configuration; struct dsi_pll_regs reg_setup;

@@ -793,8 +792,6 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) pll = &pll_7nm->base; pll->cfg = phy->cfg;

- pll_7nm->vco_delay = 1; - ret = pll_7nm_register(pll_7nm, phy->provided_clocks); if (ret) { DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret);