The configurable hdmi_ref output of the PLL block is derived from the tvdpll_594m clock signal via a configurable PLL post-divider. It is used as the PLL reference input to the HDMI PHY module.
Signed-off-by: Philipp Zabel p.zabel@pengutronix.de --- drivers/clk/mediatek/clk-mt8173.c | 5 +++++ include/dt-bindings/clock/mt8173-clk.h | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index e7b3997..fe7a91b 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -901,6 +901,11 @@ static void __init mtk_apmixedsys_init(struct device_node *node) clk_data->clks[cku->id] = clk; }
+ clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0, + base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO, + NULL); + clk_data->clks[CLK_APMIXED_HDMI_REF] = clk; + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); if (r) pr_err("%s(): could not register clock provider: %d\n", diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h index bf1302e..784e987 100644 --- a/include/dt-bindings/clock/mt8173-clk.h +++ b/include/dt-bindings/clock/mt8173-clk.h @@ -173,7 +173,8 @@ #define CLK_APMIXED_LVDSPLL 13 #define CLK_APMIXED_MSDCPLL2 14 #define CLK_APMIXED_REF2USB_TX 15 -#define CLK_APMIXED_NR_CLK 16 +#define CLK_APMIXED_HDMI_REF 16 +#define CLK_APMIXED_NR_CLK 17
/* INFRA_SYS */