On Mon, 31 Jan 2022 01:45:17 +0530, Rajeev Nandan wrote:
In most cases, the default values of DSI PHY tuning registers should be sufficient as they are fully optimized. However, in some cases where extreme board parasitics cause the eye shape to degrade, the override bits can be used to improve the signal quality.
The general guidelines for DSI PHY tuning include:
- High and moderate data rates may benefit from the drive strength and drive level tuning.
- Drive strength tuning will affect the output impedance and may be used for matching optimization.
- Drive level tuning will affect the output levels without affecting the impedance.
The clock and data lanes have a calibration circuitry feature. The drive strength tuning can be done by adjusting rescode offset for hstop/hsbot, and the drive level tuning can be done by adjusting the LDO output level for the HSTX drive.
Signed-off-by: Rajeev Nandan quic_rajeevny@quicinc.com
Changes in v2:
- More details in the commit text (Stephen Boyd)
- Use human understandable values (Stephen Boyd, Dmitry Baryshkov)
- Do not take values that are going to be unused (Dmitry Baryshkov)
Changes in v3:
- Use "qcom," prefix (Dmitry Baryshkov)
- Remove encoding from phy-drive-ldo-level (Dmitry Baryshkov)
- Use negative values instead of two's complement (Dmitry, Rob Herring)
Changes in v4:
- Fix dt_binding_check error (Rob Herring's bot)
Changes in v5:
- None
.../bindings/display/msm/dsi-phy-10nm.yaml | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+)
Reviewed-by: Rob Herring robh@kernel.org