From: Abdiel Janulgue abdiel.janulgue@linux.intel.com
LMEM can be accessed by the CPU through a BAR. The mapping itself should be 1:1.
Signed-off-by: Abdiel Janulgue abdiel.janulgue@linux.intel.com Signed-off-by: Matthew Auld matthew.auld@intel.com Cc: Joonas Lahtinen joonas.lahtinen@linux.intel.com --- drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/gem/i915_gem_lmem.h | 3 +++ 2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c index f00078ac331e..8d0251af5dfc 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c @@ -225,6 +225,22 @@ void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj, return io_mapping_map_wc(&obj->mm.region->iomap, offset, size); }
+resource_size_t i915_gem_object_lmem_io_offset(struct drm_i915_gem_object *obj, + unsigned long n) +{ + struct intel_memory_region *mem = obj->mm.region; + dma_addr_t daddr; + + /* + * XXX: It's not a dma address, more a device address or physical + * offset, so we are clearly abusing the semantics of the sg_table + * here, and elsewhere like in the gtt paths. + */ + daddr = i915_gem_object_get_dma_address(obj, n); + + return mem->io_start + daddr; +} + bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj) { struct intel_memory_region *region = obj->mm.region; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h index 31a6462bdbb6..43e6e715eeed 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h @@ -21,6 +21,9 @@ void __iomem * i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj, unsigned long n);
+resource_size_t i915_gem_object_lmem_io_offset(struct drm_i915_gem_object *obj, + unsigned long n); + bool i915_gem_object_is_lmem(struct drm_i915_gem_object *obj);
struct drm_i915_gem_object *