Hi Piotr,
On Tue, Mar 29, 2022 at 09:31:01AM +0200, Piotr Oniszczuk wrote:
Wiadomość napisana przez Sascha Hauer s.hauer@pengutronix.de w dniu 28.03.2022, o godz. 17:10:
Changes since v8:
- make hclk_vo a critical clock instead of enabling it in the hdmi driver
- Fix vop2_setup_layer_mixer(), reported by Andy Yan
- Limit planes possible_crtcs to actually existing crtcs
Sascha,
FYI: I was hoping v9 will fix green screen issue i see when video player wants to draw to nv12 capable drm plane. It look issue is still present :-(
You can easily reproduce with modetest utility:
modetest -P 43@67:1920x1080@NV12
This only sets the overlay, but how did you get something on the screen initially?
I did with "modetest -s 69@67:1920x1080 -d" and with this it works as expected, I can't reproduce any green screen issue here.
I found another problem though which might or might not be related with your issue. I saw that the overlay is not exactly centered as it ought to be. This goes down to wrong delay settings for the overlay, the following patch fixes this.
Sascha
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From f9a92401344e8aa3203fca2236dd4a40cc8690f6 Mon Sep 17 00:00:00 2001
From: Sascha Hauer s.hauer@pengutronix.de Date: Wed, 30 Mar 2022 09:22:26 +0200 Subject: [PATCH] fixup! drm: rockchip: Add VOP2 driver
--- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 69e9870d5f2dc..7dba7b9b63dc6 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1979,10 +1979,10 @@ static void vop2_setup_dly_for_windows(struct vop2 *vop2) sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly); break; case ROCKCHIP_VOP2_SMART0: - sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly); + sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly); break; case ROCKCHIP_VOP2_SMART1: - sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly); + sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly); break; } }