Add a property in device tree to control the driving by different board.
Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org Reviewed-by: Matthias Brugger matthias.bgg@gmail.com Signed-off-by: Jitao Shi jitao.shi@mediatek.com --- drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 14 ++++++++++++++ drivers/gpu/drm/mediatek/mtk_mipi_tx.h | 1 + drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 7 +++++++ 3 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c index e4d34484ecc8..e301af64809e 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c @@ -125,6 +125,20 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev) return ret; }
+ ret = of_property_read_u32(dev->of_node, "drive-strength-microamp", + &mipi_tx->mipitx_drive); + /* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */ + if (ret < 0) + mipi_tx->mipitx_drive = 4600; + + /* check the mipitx_drive valid */ + if (mipi_tx->mipitx_drive > 6000 || mipi_tx->mipitx_drive < 3000) { + dev_warn(dev, "drive-strength-microamp is invalid %d, not in 3000 ~ 6000\n", + mipi_tx->mipitx_drive); + mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000, + 6000); + } + ref_clk_name = __clk_get_name(ref_clk);
ret = of_property_read_string(dev->of_node, "clock-output-names", diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h index 413f35d86219..eea44327fe9f 100644 --- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.h +++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.h @@ -27,6 +27,7 @@ struct mtk_mipi_tx { struct device *dev; void __iomem *regs; u32 data_rate; + u32 mipitx_drive; const struct mtk_mipitx_data *driver_data; struct clk_hw pll_hw; struct clk *pll; diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c index 91f08a351fd0..e4cc967750cb 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c @@ -17,6 +17,9 @@ #define RG_DSI_BG_CORE_EN BIT(7) #define RG_DSI_PAD_TIEL_SEL BIT(8)
+#define MIPITX_VOLTAGE_SEL 0x0010 +#define RG_DSI_HSTX_LDO_REF_SEL (0xf << 6) + #define MIPITX_PLL_PWR 0x0028 #define MIPITX_PLL_CON0 0x002c #define MIPITX_PLL_CON1 0x0030 @@ -123,6 +126,10 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
+ mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL, + RG_DSI_HSTX_LDO_REF_SEL, + (mipi_tx->mipitx_drive - 3000) / 200 << 6); + mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); }