* Tony Lindgren tony@atomide.com [200303 15:14]:
- Tomi Valkeinen tomi.valkeinen@ti.com [200303 06:03]:
On 24/02/2020 21:12, Tony Lindgren wrote:
- if (sysc_soc->soc == SOC_3430) {
/* Clear DSS_SDI_CONTROL */sysc_write(ddata, dispc_offset + 0x44, 0);/* Clear DSS_PLL_CONTROL */sysc_write(ddata, dispc_offset + 0x48, 0);These are not dispc registers, but dss registers.
Ouch. Thanks for catching this, will include in the fix.
- }
- /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
- sysc_write(ddata, dispc_offset + 0x40, 0);
Same here.
Below is a fix using dispc offset for dss registers.
Regards,
Tony
8< ----------------------
From tony Mon Sep 17 00:00:00 2001
From: Tony Lindgren tony@atomide.com Date: Tue, 3 Mar 2020 07:17:43 -0800 Subject: [PATCH] bus: ti-sysc: Fix wrong offset for display subsystem reset quirk
Commit 7324a7a0d5e2 ("bus: ti-sysc: Implement display subsystem reset quirk") added support for DSS reset, but is using dispc offset also for DSS also registers as reported by Tomi Valkeinen tomi.valkeinen@ti.com. Also, we're not using dispc_offset for dispc IRQSTATUS register so let's fix that too.
Fixes: 7324a7a0d5e2 ("bus: ti-sysc: Implement display subsystem reset quirk") Reported-by: Tomi Valkeinen tomi.valkeinen@ti.com Signed-off-by: Tony Lindgren tony@atomide.com --- drivers/bus/ti-sysc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1566,7 +1566,7 @@ static void sysc_pre_reset_quirk_dss(struct sysc *ddata) return;
/* Clear IRQSTATUS */ - sysc_write(ddata, 0x1000 + 0x18, irq_mask); + sysc_write(ddata, dispc_offset + 0x18, irq_mask);
/* Disable outputs */ val = sysc_quirk_dispc(ddata, dispc_offset, true); @@ -1580,14 +1580,14 @@ static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
if (sysc_soc->soc == SOC_3430) { /* Clear DSS_SDI_CONTROL */ - sysc_write(ddata, dispc_offset + 0x44, 0); + sysc_write(ddata, 0x44, 0);
/* Clear DSS_PLL_CONTROL */ - sysc_write(ddata, dispc_offset + 0x48, 0); + sysc_write(ddata, 0x48, 0); }
/* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ - sysc_write(ddata, dispc_offset + 0x40, 0); + sysc_write(ddata, 0x40, 0); }
/* 1-wire needs module's internal clocks enabled for reset */