-----Original Message----- From: dri-devel dri-devel-bounces@lists.freedesktop.org On Behalf Of Rob Herring Sent: Tuesday, October 13, 2020 8:43 AM To: Chrisanthus, Anitha anitha.chrisanthus@intel.com Cc: devicetree@vger.kernel.org; Neil Armstrong narmstrong@baylibre.com; Dea, Edmund J edmund.j.dea@intel.com; dri-devel@lists.freedesktop.org; Vetter, Daniel daniel.vetter@intel.com; sam@ravnborg.org Subject: Re: [PATCH v9 1/5] dt-bindings: display: Add support for Intel KeemBay Display
On Tue, Oct 13, 2020 at 12:24:38AM +0000, Chrisanthus, Anitha wrote:
Hi Neil,
Thanks for your review, please see my reply inline.
-----Original Message----- From: Neil Armstrong narmstrong@baylibre.com Sent: Friday, October 9, 2020 2:10 AM To: Chrisanthus, Anitha anitha.chrisanthus@intel.com; dri- devel@lists.freedesktop.org; devicetree@vger.kernel.org; Vetter, Daniel daniel.vetter@intel.com Cc: Dea, Edmund J edmund.j.dea@intel.com; sam@ravnborg.org Subject: Re: [PATCH v9 1/5] dt-bindings: display: Add support for Intel KeemBay Display
Hi,
On 09/10/2020 03:03, Anitha Chrisanthus wrote:
This patch adds bindings for Intel KeemBay Display
v2: review changes from Rob Herring
Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com
.../bindings/display/intel,keembay-display.yaml | 99
++++++++++++++++++++++
1 file changed, 99 insertions(+) create mode 100644
Documentation/devicetree/bindings/display/intel,keembay-display.yaml
diff --git a/Documentation/devicetree/bindings/display/intel,keembay-
display.yaml b/Documentation/devicetree/bindings/display/intel,keembay- display.yaml
new file mode 100644 index 0000000..a38493d --- /dev/null +++ b/Documentation/devicetree/bindings/display/intel,keembay-
display.yaml
@@ -0,0 +1,99 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/intel,keembay-
display.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Devicetree bindings for Intel Keem Bay display controller
+maintainers:
- Anitha Chrisanthus anitha.chrisanthus@intel.com
- Edmond J Dea edmund.j.dea@intel.com
+properties:
- compatible:
- const: intel,kmb_display
- reg:
- items:
- description: Lcd registers range- description: Mipi registers rangeLooking at the registers, the MIPI transceiver seems to be a separate IP, same for D-PHY which should have a proper PHY driver instead of beeing handled here.
The LCD, MIPI DSI, DPHY and MSSCAM as a group, are considered the display subsystem for Keem Bay. As such, there are several interdependencies that make splitting them up next to impossible and
Please detail what those inter-dependencies are. It's doubtful that you have anything we have not had to deal with in other SoCs.
currently we do not have the resources available for that effort.
That is certainly not justification for accepting this.
Rob
Hi Rob, the wording was probably a bit exaggerated and you're right in that there it's not unique from a hardware perspective.
The problem we have (and I know, it's our problem, not yours) is that our program required us to develop this internally first and then try to upstream it. So now that we've put a large effort into developing and testing the driver, it's very difficult for us to justify the resources to re-design it to better match the design of other SOC display drivers.
We did review other SOC display drivers before creating this and thought that we were following the best practices for the design.
I fully agree that lack of resources is not justification for not fixing something broken. But on the flip side, neither is changing the design because it could be "better" justification for not accepting it.
If there is something wrong with the driver and it will cause problems in the future, then please, let us know. That would provide the data needed to justify additional effort.
Bob
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