On 04/18/2017 04:38 PM, Eric Anholt wrote:
For the Raspberry Pi's bindings, the power domain also implicitly turns on the clock and deasserts reset, but for the new Cygnus port we start representing the clock in the devicetree.
v2: Document the clock-names property, check for -ENOENT for no clock in DT.
Signed-off-by: Eric Anholt eric@anholt.net
- if (v3d->clk)
clk_disable_unprepare(v3d->clk);
The clock API allows you to pass a NULL clk and do nothing in these cases which is what you seem to have done a few lines below, you could simplify these checks?
- return 0;
}
@@ -318,6 +322,13 @@ static int vc4_v3d_runtime_resume(struct device *dev) if (ret) return ret;
- if (v3d->clk) {
int ret = clk_prepare_enable(v3d->clk);
if (ret != 0)
return ret;
- }
- vc4_v3d_init_hw(vc4->dev); vc4_irq_postinstall(vc4->dev);
@@ -348,15 +359,40 @@ static int vc4_v3d_bind(struct device *dev, struct device *master, void *data) vc4->v3d = v3d; v3d->vc4 = vc4;
v3d->clk = devm_clk_get(dev, "v3d_clk");
if (IS_ERR(v3d->clk)) {
int ret = PTR_ERR(v3d->clk);
if (ret == -ENOENT) {
/* bcm2835 didn't have a clock reference in the DT. */
ret = 0;
v3d->clk = NULL;
} else {
if (ret != -EPROBE_DEFER)
dev_err(dev, "Failed to get V3D clock: %d\n",
ret);
return ret;
}
}
if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) { DRM_ERROR("V3D_IDENT0 read 0x%08x instead of 0x%08x\n", V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0); return -EINVAL; }
if (v3d->clk) {
ret = clk_prepare_enable(v3d->clk);
if (ret != 0)
return ret;
}
ret = vc4_allocate_bin_bo(drm);
- if (ret)
if (ret) {
if (v3d->clk)
clk_disable_unprepare(v3d->clk);
return ret;
}
/* Reset the binner overflow address/size at setup, to be sure
- we don't reuse an old one.