MMUv2 supports up to 40 bits of physical address by folding the upper 8 bits into bits [4:11] of the PTE.
Signed-off-by: Lucas Stach l.stach@pengutronix.de --- drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c b/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c index 2d9d09608bc2..f2e4fa773e22 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_iommu_v2.c @@ -87,11 +87,14 @@ static int etnaviv_iommuv2_map(struct etnaviv_iommu_domain *domain, struct etnaviv_iommuv2_domain *etnaviv_domain = to_etnaviv_domain(domain); int mtlb_entry, stlb_entry, ret; - u32 entry = (u32)paddr | MMUv2_PTE_PRESENT; + u32 entry = lower_32_bits(paddr) | MMUv2_PTE_PRESENT;
if (size != SZ_4K) return -EINVAL;
+ if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) + entry |= (upper_32_bits(paddr) & 0xff) << 4; + if (prot & ETNAVIV_PROT_WRITE) entry |= MMUv2_PTE_WRITEABLE;