-----Original Message----- From: Intel-gfx intel-gfx-bounces@lists.freedesktop.org On Behalf Of Jani Nikula Sent: Tuesday, August 31, 2021 7:48 PM To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org; ville.syrjala@linux.intel.com; Nikula, Jani jani.nikula@intel.com Subject: [Intel-gfx] [PATCH v2 5/6] drm/i915/edp: postpone MSO init until after EDID read
MSO will require segment pixel overlap information from the EDID. Postpone MSO init until after we've read and cached the EDID.
Looks ok to me. Reviewed-by: Uma Shankar uma.shankar@intel.com
Signed-off-by: Jani Nikula jani.nikula@intel.com
drivers/gpu/drm/i915/display/intel_dp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 64e8151d13a4..df402f63b741 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2536,8 +2536,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) */ intel_edp_init_source_oui(intel_dp, true);
- intel_edp_mso_init(intel_dp);
- return true;
}
@@ -4804,6 +4802,9 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, if (fixed_mode) downclock_mode = intel_drrs_init(intel_connector, fixed_mode);
- /* MSO requires information from the EDID */
- intel_edp_mso_init(intel_dp);
- /* multiply the mode clock and horizontal timings for MSO */ intel_edp_mso_mode_fixup(intel_connector, fixed_mode); intel_edp_mso_mode_fixup(intel_connector, downclock_mode);
-- 2.30.2