v2: code review changes Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com --- drivers/gpu/drm/kmb/kmb_plane.c | 14 +++++++++++++- drivers/gpu/drm/kmb/kmb_regs.h | 1 + 2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/kmb/kmb_plane.c b/drivers/gpu/drm/kmb/kmb_plane.c index 74a3573..cb05cb8 100644 --- a/drivers/gpu/drm/kmb/kmb_plane.c +++ b/drivers/gpu/drm/kmb/kmb_plane.c @@ -208,7 +208,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, unsigned int dma_len; struct kmb_plane *kmb_plane = to_kmb_plane(plane); unsigned int dma_cfg; - unsigned int ctrl = 0, val = 0; + unsigned int ctrl = 0, val = 0, out_format = 0; unsigned int src_w, src_h, crtc_x, crtc_y; unsigned char plane_id = kmb_plane->id;
@@ -279,6 +279,18 @@ static void kmb_plane_atomic_update(struct drm_plane *plane, /* enable DMA */ kmb_write(lcd, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg);
+ /* FIXME no doc on how to set output format - may need to change + * this later + */ + if (val & LCD_LAYER_BGR_ORDER) + out_format |= LCD_OUTF_BGR_ORDER; + else if (val & LCD_LAYER_CRCB_ORDER) + out_format |= LCD_OUTF_CRCB_ORDER; + /* do not interleave RGB channels for mipi Tx compatibility */ + out_format |= LCD_OUTF_MIPI_RGB_MODE; + /* pixel format from LCD_LAYER_CFG */ + out_format |= ((val >> 9) & 0x1F); + kmb_write(lcd, LCD_OUT_FORMAT_CFG, out_format); }
static const struct drm_plane_helper_funcs kmb_plane_helper_funcs = { diff --git a/drivers/gpu/drm/kmb/kmb_regs.h b/drivers/gpu/drm/kmb/kmb_regs.h index 8346a04..8b67f2b 100644 --- a/drivers/gpu/drm/kmb/kmb_regs.h +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -320,6 +320,7 @@ #define LCD_OUTF_BGR_ORDER (1 << 5) #define LCD_OUTF_Y_ORDER (1 << 6) #define LCD_OUTF_CRCB_ORDER (1 << 7) +#define LCD_OUTF_MIPI_RGB_MODE (1 << 18)
#define LCD_HSYNC_WIDTH (0x4 * 0x801) #define LCD_H_BACKPORCH (0x4 * 0x802)