Dave Emett david.emett@broadcom.com writes:
On Mon, 3 Dec 2018 at 17:22, Dave Emett david.emett@broadcom.com wrote:
- The caches (L1T, slice, and L2T) will be flushed before the job
- executes. The TLB writes are guaranteed to have been flushed by
I would say before *each* job executes, as the caches are flushed before both bin and render. I wouldn't say "the caches" as not all of the V3D caches are flushed before executing a control list. In particular, the VCD cache is not cleared by the kernel driver (not even sure if there is a register interface to do this); it is expected that the control list will do this itself (using the CLEAR_VCD_CACHE instruction). On 3.3 and earlier there is a separate L2C for instructions/uniforms and a GCA. These do need to be flushed, and it looks like they are, so they should be mentioned here.
Correction: on *3.2* and earlier there is a separate L2C for instructions/uniforms. On 3.3 and earlier there is a GCA.
It looks like we're currently unconditionally writing the L2C clear registers. We should really only be doing this on 3.2 and earlier.
OK, I've pushed the timeline name and tracing to drm-misc-next, and I'll resend the rest with more comments and the L2C change and outside-in invalidation once I'm far enough into this CTS run that I'm confident.