14 Apr
2022
14 Apr
'22
2:15 a.m.
From: Wang, Zhi A zhi.a.wang@intel.com Sent: Thursday, April 14, 2022 5:09 AM
Or is it that only the page table levels themselves are GFNs and the actual DMA's are IOVA? The unclear mixing of GFN as IOVA in the code makes it inscrutible.
No. Even the HW is capable of controlling the level of translation, but it's not used like this in the existing driver. It's definitely an architecture open.
There is no open on this. Any guest memory that vGPU accesses must be IOVA including page table levels. There is only one address space per vRID.