[RFC 8/21] DRM: Add VIA drm driver

commit 33c7dca3f212ef8dff75312e1e4044fb1bcae898 Author: James Simmons jsimmons@infradead.org Date: Sat Jun 8 09:24:11 2013 -0400

via: Display register tables and engine register definitions

The via_disp_reg.h contains tables that define the registers and their bit fields we need for various resolution settings or property handing (i.e scaling). The second header via_regs.h contains convient names for registers relating to the graphic engines. We also update the command verifier to handle these changes. More 3D register definitions are added to via_3d_reg.h.

Signed-Off-by: James Simmons jsimmons@infradead.org

diff --git a/drivers/gpu/drm/via/via_3d_reg.h b/drivers/gpu/drm/via/via_3d_reg.h index 462375d..e42705b 100644 --- a/drivers/gpu/drm/via/via_3d_reg.h +++ b/drivers/gpu/drm/via/via_3d_reg.h @@ -1,6 +1,6 @@ /* - * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. - * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * Copyright 1998-2011 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2011 S3 Graphics, Inc. All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -16,7 +16,7 @@ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. @@ -50,6 +50,7 @@ #define HC_ParaType_Palette 0x0003 #define HC_ParaType_PreCR 0x0010 #define HC_ParaType_Auto 0x00fe +#define INV_ParaType_Dummy 0x00300000

/* Transmission Space */ @@ -176,7 +177,7 @@ /* Command * Command A */ -#define HC_HCmdHeader_MASK 0xfe000000 /*0xffe00000 */ +#define HC_HCmdHeader_MASK 0xfe000000 /*0xffe00000 */ #define HC_HE3Fire_MASK 0x00100000 #define HC_HPMType_MASK 0x000f0000 #define HC_HEFlag_MASK 0x0000e000 @@ -236,6 +237,8 @@ /* Enable Setting */ #define HC_SubA_HEnable 0x0000 +#define HC_HenForce1P_MASK 0x00800000 //[Force 1 Pipe] +#define HC_HenZDCheck_MASK 0x00400000 //[Z dirty bit settings] #define HC_HenTXEnvMap_MASK 0x00200000 #define HC_HenVertexCNT_MASK 0x00100000 #define HC_HenCPUDAZ_MASK 0x00080000 @@ -684,6 +687,12 @@

/* Texture subtype definitions */ +#define HC_SubType_Samp0 0x00000020 +#define HC_SubType_Samp1 0x00000021 + + +/* Texture subtype definitions + */ #define HC_SubType_Tex0 0x00000000 #define HC_SubType_Tex1 0x00000001 #define HC_SubType_TexGeneral 0x000000fe @@ -762,7 +771,13 @@ #define HC_SubA_HTXnBumpM10 0x0092 #define HC_SubA_HTXnBumpM11 0x0093 #define HC_SubA_HTXnLScale 0x0094 -#define HC_SubA_HTXSMD 0x0000 + +#define HC_SubA_HTXSMD 0x0000 +#define HC_SubA_HTXYUV2RGB1 0x0001 +#define HC_SubA_HTXYUV2RGB2 0x0002 +#define HC_SubA_HTXYUV2RGB3 0x0003 +#define HTXYUV2RGB4BT601 (1<<23) +#define HTXYUV2RGB4BT709 (1<<22) /* HC_SubA_HTXnL012BasH 0x0020 */ #define HC_HTXnL0BasH_MASK 0x000000ff @@ -965,6 +980,7 @@ #define HC_HTXnFM_Lum 0x00100000 #define HC_HTXnFM_Alpha 0x00180000 #define HC_HTXnFM_DX 0x00280000 +#define HC_HTXnFM_YUV 0x00300000 #define HC_HTXnFM_ARGB16 0x00880000 #define HC_HTXnFM_ARGB32 0x00980000 #define HC_HTXnFM_ABGR16 0x00a80000 @@ -995,6 +1011,12 @@ #define HC_HTXnFM_DX1 (HC_HTXnFM_DX | 0x00010000) #define HC_HTXnFM_DX23 (HC_HTXnFM_DX | 0x00020000) #define HC_HTXnFM_DX45 (HC_HTXnFM_DX | 0x00030000) +//YUV package mode +#define HC_HTXnFM_YUY2 (HC_HTXnFM_YUV | 0x00000000) +//YUV planner mode +#define HC_HTXnFM_YV12 (HC_HTXnFM_YUV | 0x00040000) +//YUV planner mode +#define HC_HTXnFM_IYUV (HC_HTXnFM_YUV | 0x00040000) #define HC_HTXnFM_RGB555 (HC_HTXnFM_ARGB16 | 0x00000000) #define HC_HTXnFM_RGB565 (HC_HTXnFM_ARGB16 | 0x00010000) #define HC_HTXnFM_ARGB1555 (HC_HTXnFM_ARGB16 | 0x00020000) @@ -1023,6 +1045,13 @@ #define HC_HTXnLoc_Local 0x00000000 #define HC_HTXnLoc_Sys 0x00000002 #define HC_HTXnLoc_AGP 0x00000003 + +// Video Texture +#define HC_HTXnYUV2RGBMode_RGB 0x00000000 +#define HC_HTXnYUV2RGBMode_SDTV 0x00000001 +#define HC_HTXnYUV2RGBMode_HDTV 0x00000002 +#define HC_HTXnYUV2RGBMode_TABLE 0x00000003 + /* HC_SubA_HTXnTRAH 0x007f */ #define HC_HTXnTRAH_MASK 0x00ff0000 @@ -1330,9 +1359,9 @@ */ #define HC_HFthRTXA_MASK 0x000000ff

-/****************************************************************************** +/**************************************************************************** ** Define the Halcyon Internal register access constants. For simulator only. -******************************************************************************/ +****************************************************************************/ #define HC_SIMA_HAGPBstL 0x0000 #define HC_SIMA_HAGPBendL 0x0001 #define HC_SIMA_HAGPCMNT 0x0002 @@ -1477,80 +1506,154 @@ #define HC_SIMA_TX0TX1_OFF 0x0050 /*---- start of texture 1 setting ---- */ -#define HC_SIMA_HTX1L0BasL (HC_SIMA_HTX0L0BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L1BasL (HC_SIMA_HTX0L1BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L2BasL (HC_SIMA_HTX0L2BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L3BasL (HC_SIMA_HTX0L3BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L4BasL (HC_SIMA_HTX0L4BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L5BasL (HC_SIMA_HTX0L5BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L6BasL (HC_SIMA_HTX0L6BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L7BasL (HC_SIMA_HTX0L7BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L8BasL (HC_SIMA_HTX0L8BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L9BasL (HC_SIMA_HTX0L9BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LaBasL (HC_SIMA_HTX0LaBasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LbBasL (HC_SIMA_HTX0LbBasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LcBasL (HC_SIMA_HTX0LcBasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LdBasL (HC_SIMA_HTX0LdBasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LeBasL (HC_SIMA_HTX0LeBasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LfBasL (HC_SIMA_HTX0LfBasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L10BasL (HC_SIMA_HTX0L10BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L11BasL (HC_SIMA_HTX0L11BasL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L012BasH (HC_SIMA_HTX0L012BasH + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L345BasH (HC_SIMA_HTX0L345BasH + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L678BasH (HC_SIMA_HTX0L678BasH + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L9abBasH (HC_SIMA_HTX0L9abBasH + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LcdeBasH (HC_SIMA_HTX0LcdeBasH + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1Lf1011BasH (HC_SIMA_HTX0Lf1011BasH + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L0Pit (HC_SIMA_HTX0L0Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L1Pit (HC_SIMA_HTX0L1Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L2Pit (HC_SIMA_HTX0L2Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L3Pit (HC_SIMA_HTX0L3Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L4Pit (HC_SIMA_HTX0L4Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L5Pit (HC_SIMA_HTX0L5Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L6Pit (HC_SIMA_HTX0L6Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L7Pit (HC_SIMA_HTX0L7Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L8Pit (HC_SIMA_HTX0L8Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L9Pit (HC_SIMA_HTX0L9Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LaPit (HC_SIMA_HTX0LaPit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LbPit (HC_SIMA_HTX0LbPit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LcPit (HC_SIMA_HTX0LcPit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LdPit (HC_SIMA_HTX0LdPit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LePit (HC_SIMA_HTX0LePit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LfPit (HC_SIMA_HTX0LfPit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L10Pit (HC_SIMA_HTX0L10Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L11Pit (HC_SIMA_HTX0L11Pit + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L0_5WE (HC_SIMA_HTX0L0_5WE + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L6_bWE (HC_SIMA_HTX0L6_bWE + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1Lc_11WE (HC_SIMA_HTX0Lc_11WE + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L0_5HE (HC_SIMA_HTX0L0_5HE + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L6_bHE (HC_SIMA_HTX0L6_bHE + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1Lc_11HE (HC_SIMA_HTX0Lc_11HE + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1L0OS (HC_SIMA_HTX0L0OS + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TB (HC_SIMA_HTX0TB + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1MPMD (HC_SIMA_HTX0MPMD + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1CLODu (HC_SIMA_HTX0CLODu + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1FM (HC_SIMA_HTX0FM + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TRCH (HC_SIMA_HTX0TRCH + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TRCL (HC_SIMA_HTX0TRCL + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBC (HC_SIMA_HTX0TBC + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TRAH (HC_SIMA_HTX0TRAH + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LTC (HC_SIMA_HTX0LTC + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LTA (HC_SIMA_HTX0LTA + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBLCsat (HC_SIMA_HTX0TBLCsat + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBLCop (HC_SIMA_HTX0TBLCop + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBLMPfog (HC_SIMA_HTX0TBLMPfog + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBLAsat (HC_SIMA_HTX0TBLAsat + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBLRCa (HC_SIMA_HTX0TBLRCa + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBLRCb (HC_SIMA_HTX0TBLRCb + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBLRCc (HC_SIMA_HTX0TBLRCc + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBLRCbias (HC_SIMA_HTX0TBLRCbias + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBLRAa (HC_SIMA_HTX0TBLRAa + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1TBLRFog (HC_SIMA_HTX0TBLRFog + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1BumpM00 (HC_SIMA_HTX0BumpM00 + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1BumpM01 (HC_SIMA_HTX0BumpM01 + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1BumpM10 (HC_SIMA_HTX0BumpM10 + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1BumpM11 (HC_SIMA_HTX0BumpM11 + HC_SIMA_TX0TX1_OFF) -#define HC_SIMA_HTX1LScale (HC_SIMA_HTX0LScale + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0BasL \ + (HC_SIMA_HTX0L0BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L1BasL \ + (HC_SIMA_HTX0L1BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L2BasL \ + (HC_SIMA_HTX0L2BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L3BasL \ + (HC_SIMA_HTX0L3BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L4BasL (\ + HC_SIMA_HTX0L4BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L5BasL \ + (HC_SIMA_HTX0L5BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6BasL \ + (HC_SIMA_HTX0L6BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L7BasL \ + (HC_SIMA_HTX0L7BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L8BasL \ + (HC_SIMA_HTX0L8BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9BasL \ + (HC_SIMA_HTX0L9BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LaBasL \ + (HC_SIMA_HTX0LaBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LbBasL \ + (HC_SIMA_HTX0LbBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcBasL \ + (HC_SIMA_HTX0LcBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LdBasL \ + (HC_SIMA_HTX0LdBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LeBasL \ + (HC_SIMA_HTX0LeBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LfBasL \ + (HC_SIMA_HTX0LfBasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L10BasL \ + (HC_SIMA_HTX0L10BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L11BasL \ + (HC_SIMA_HTX0L11BasL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L012BasH \ + (HC_SIMA_HTX0L012BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L345BasH \ + (HC_SIMA_HTX0L345BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L678BasH \ + (HC_SIMA_HTX0L678BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9abBasH \ + (HC_SIMA_HTX0L9abBasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcdeBasH \ + (HC_SIMA_HTX0LcdeBasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lf1011BasH \ + (HC_SIMA_HTX0Lf1011BasH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0Pit \ + (HC_SIMA_HTX0L0Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L1Pit \ + (HC_SIMA_HTX0L1Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L2Pit \ + (HC_SIMA_HTX0L2Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L3Pit \ + (HC_SIMA_HTX0L3Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L4Pit \ + (HC_SIMA_HTX0L4Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L5Pit \ + (HC_SIMA_HTX0L5Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6Pit \ + (HC_SIMA_HTX0L6Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L7Pit \ + (HC_SIMA_HTX0L7Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L8Pit \ + (HC_SIMA_HTX0L8Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L9Pit \ + (HC_SIMA_HTX0L9Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LaPit \ + (HC_SIMA_HTX0LaPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LbPit \ + (HC_SIMA_HTX0LbPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LcPit \ + (HC_SIMA_HTX0LcPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LdPit \ + (HC_SIMA_HTX0LdPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LePit \ + (HC_SIMA_HTX0LePit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LfPit \ + (HC_SIMA_HTX0LfPit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L10Pit \ + (HC_SIMA_HTX0L10Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L11Pit \ + (HC_SIMA_HTX0L11Pit + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0_5WE \ + (HC_SIMA_HTX0L0_5WE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6_bWE \ + (HC_SIMA_HTX0L6_bWE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lc_11WE \ + (HC_SIMA_HTX0Lc_11WE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0_5HE \ + (HC_SIMA_HTX0L0_5HE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L6_bHE \ + (HC_SIMA_HTX0L6_bHE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1Lc_11HE \ + (HC_SIMA_HTX0Lc_11HE + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1L0OS \ + (HC_SIMA_HTX0L0OS + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TB \ + (HC_SIMA_HTX0TB + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1MPMD \ + (HC_SIMA_HTX0MPMD + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1CLODu \ + (HC_SIMA_HTX0CLODu + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1FM \ + (HC_SIMA_HTX0FM + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRCH \ + (HC_SIMA_HTX0TRCH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRCL \ + (HC_SIMA_HTX0TRCL + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBC \ + (HC_SIMA_HTX0TBC + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TRAH \ + (HC_SIMA_HTX0TRAH + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LTC \ + (HC_SIMA_HTX0LTC + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LTA \ + (HC_SIMA_HTX0LTA + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLCsat \ + (HC_SIMA_HTX0TBLCsat + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLCop \ + (HC_SIMA_HTX0TBLCop + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLMPfog \ + (HC_SIMA_HTX0TBLMPfog + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLAsat \ + (HC_SIMA_HTX0TBLAsat + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCa \ + (HC_SIMA_HTX0TBLRCa + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCb \ + (HC_SIMA_HTX0TBLRCb + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCc \ + (HC_SIMA_HTX0TBLRCc + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRCbias \ + (HC_SIMA_HTX0TBLRCbias + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRAa \ + (HC_SIMA_HTX0TBLRAa + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1TBLRFog \ + (HC_SIMA_HTX0TBLRFog + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM00 \ + (HC_SIMA_HTX0BumpM00 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM01 \ + (HC_SIMA_HTX0BumpM01 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM10 \ + (HC_SIMA_HTX0BumpM10 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1BumpM11 \ + (HC_SIMA_HTX0BumpM11 + HC_SIMA_TX0TX1_OFF) +#define HC_SIMA_HTX1LScale \ + (HC_SIMA_HTX0LScale + HC_SIMA_TX0TX1_OFF) /*---- end of texture 1 setting ---- 0xaf */ #define HC_SIMA_HTXSMD 0x00b0 @@ -1580,9 +1683,9 @@ #define HC_SIMA_HRErr 0x0445 #define HC_SIMA_FIFOstatus 0x0446

-/****************************************************************************** +/**************************************************************************** ** Define the AGP command header. -******************************************************************************/ +****************************************************************************/ #define HC_ACMD_MASK 0xfe000000 #define HC_ACMD_SUB_MASK 0x0c000000 #define HC_ACMD_HCmdA 0xee000000 @@ -1605,18 +1708,18 @@ #define HC_ACMD_H4COUNT_MASK 0x01fffe00 #define HC_ACMD_H4COUNT_SHIFT 9

-/******************************************************************************** +/***************************************************************************** ** Define Header -********************************************************************************/ -#define HC_HEADER2 0xF210F110 +*****************************************************************************/ +#define HC_HEADER2 0xF210F110

-/******************************************************************************** +/***************************************************************************** ** Define Dummy Value -********************************************************************************/ -#define HC_DUMMY 0xCCCCCCCC -/******************************************************************************** +*****************************************************************************/ +#define HC_DUMMY 0xCCCCCCCC +/***************************************************************************** ** Define for DMA use -********************************************************************************/ +*****************************************************************************/ #define HALCYON_HEADER2 0XF210F110 #define HALCYON_FIRECMD 0XEE100000 #define HALCYON_FIREMASK 0XFFF00000 @@ -1643,8 +1746,118 @@ #define HC_HAGPBpID_STOP 0x00000002 #define HC_HAGPBpH_MASK 0x00ffffff

+ #define VIA_VIDEO_HEADER5 0xFE040000 #define VIA_VIDEO_HEADER6 0xFE050000 #define VIA_VIDEO_HEADER7 0xFE060000 #define VIA_VIDEOMASK 0xFFFF0000 + +/***************************************************************************** +** Define for H5 DMA use +*****************************************************************************/ +#define H5_HC_DUMMY 0xCC000000 + +/* Command Header Type */ +#define INV_DUMMY_MASK 0xFF000000 +#define INV_AGPHeader0 0xFE000000 +#define INV_AGPHeader1 0xFE010000 +#define INV_AGPHeader2 0xFE020000 +#define INV_AGPHeader3 0xFE030000 +#define INV_AGPHeader4 0xFE040000 +#define INV_AGPHeader5 0xFE050000 +#define INV_AGPHeader6 0xFE060000 +#define INV_AGPHeader7 0xFE070000 +#define INV_AGPHeader9 0xFE090000 +#define INV_AGPHeaderA 0xFE0A0000 +#define INV_AGPHeader40 0xFE400000 +#define INV_AGPHeader41 0xFE410000 +#define INV_AGPHeader43 0xFE430000 +#define INV_AGPHeader45 0xFE450000 +#define INV_AGPHeader47 0xFE470000 +#define INV_AGPHeader4A 0xFE4A0000 +#define INV_AGPHeader82 0xFE820000 +#define INV_AGPHeader83 0xFE830000 +#define INV_AGPHeader_MASK 0xFFFF0000 +#define INV_AGPHeader2A 0xFE2A0000 +#define INV_AGPHeader25 0xFE250000 +#define INV_AGPHeader20 0xFE200000 +#define INV_AGPHeader23 0xFE230000 +#define INV_AGPHeaderE2 0xFEE20000 +#define INV_AGPHeaderE3 0xFEE30000 + +/*Transmission IO Space*/ +#define INV_REG_CR_TRANS 0x041C +#define INV_REG_CR_BEGIN 0x0420 +#define INV_REG_CR_END 0x0438 + +#define INV_REG_3D_TRANS 0x043C +#define INV_REG_3D_BEGIN 0x0440 +#define INV_REG_3D_END 0x06FC + +#define INV_ParaType_CmdVdata 0x0000 + +/* H5 Enable Setting + */ +#define INV_HC_SubA_HEnable1 0x00 + +#define INV_HC_HenAT4ALLRT_MASK 0x00100000 +#define INV_HC_HenATMRT3_MASK 0x00080000 +#define INV_HC_HenATMRT2_MASK 0x00040000 +#define INV_HC_HenATMRT1_MASK 0x00020000 +#define INV_HC_HenATMRT0_MASK 0x00010000 +#define INV_HC_HenSCMRT3_MASK 0x00008000 +#define INV_HC_HenSCMRT2_MASK 0x00004000 +#define INV_HC_HenSCMRT1_MASK 0x00002000 +#define INV_HC_HenSCMRT0_MASK 0x00001000 +#define INV_HC_HenFOGMRT3_MASK 0x00000800 +#define INV_HC_HenFOGMRT2_MASK 0x00000400 +#define INV_HC_HenFOGMRT1_MASK 0x00000200 +#define INV_HC_HenFOGMRT0_MASK 0x00000100 +#define INV_HC_HenABLMRT3_MASK 0x00000080 +#define INV_HC_HenABLMRT2_MASK 0x00000040 +#define INV_HC_HenABLMRT1_MASK 0x00000020 +#define INV_HC_HenABLMRT0_MASK 0x00000010 +#define INV_HC_HenDTMRT3_MASK 0x00000008 +#define INV_HC_HenDTMRT2_MASK 0x00000004 +#define INV_HC_HenDTMRT1_MASK 0x00000002 +#define INV_HC_HenDTMRT0_MASK 0x00000001 + +#define INV_HC_SubA_HEnable2 0x01 + +#define INV_HC_HenLUL2DR_MASK 0x00800000 +#define INV_HC_HenLDIAMOND_MASK 0x00400000 +#define INV_HC_HenPSPRITE_MASK 0x00200000 +#define INV_HC_HenC2S_MASK 0x00100000 +#define INV_HC_HenFOGPP_MASK 0x00080000 +#define INV_HC_HenSCPP_MASK 0x00040000 +#define INV_HC_HenCPP_MASK 0x00020000 +#define INV_HC_HenCZ_MASK 0x00002000 +#define INV_HC_HenVC_MASK 0x00001000 +#define INV_HC_HenCL_MASK 0x00000800 +#define INV_HC_HenPS_MASK 0x00000400 +#define INV_HC_HenWCZ_MASK 0x00000200 +#define INV_HC_HenTXCH_MASK 0x00000100 +#define INV_HC_HenBFCULL_MASK 0x00000080 +#define INV_HC_HenCW_MASK 0x00000040 +#define INV_HC_HenAA_MASK 0x00000020 +#define INV_HC_HenST_MASK 0x00000010 +#define INV_HC_HenZT_MASK 0x00000008 +#define INV_HC_HenZW_MASK 0x00000004 +#define INV_HC_HenSP_MASK 0x00000002 +#define INV_HC_HenLP_MASK 0x00000001 + +/* H5 Miscellaneous Settings + */ +#define INV_HC_SubA_HCClipTL 0x0080 +#define INV_HC_SubA_HCClipBL 0x0081 +#define INV_HC_SubA_HSClipTL 0x0082 +#define INV_HC_SubA_HSClipBL 0x0083 +#define INV_HC_SubA_HSolidCL 0x0086 +#define INV_HC_SubA_HSolidCH 0x0087 +#define INV_HC_SubA_HGBClipGL 0x0088 +#define INV_HC_SubA_HGBClipGR 0x0089 + + +#define INV_HC_ParaType_Vetex 0x00040000 + #endif diff --git a/drivers/gpu/drm/via/via_disp_reg.h b/drivers/gpu/drm/via/via_disp_reg.h new file mode 100644 index 0000000..7fa8e1a --- /dev/null +++ b/drivers/gpu/drm/via/via_disp_reg.h @@ -0,0 +1,484 @@ +/* + * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2009 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef __VIA_DISP_REG_H__ +#define __VIA_DISP_REG_H__ + +/********************************************************/ +/* Definition IGA Design Method of FIFO Registers */ +/********************************************************/ +#define IGA1_FIFO_DEPTH_SELECT_FORMULA(x) ((x / 2) - 1) +#define IGA2_FIFO_DEPTH_SELECT_FORMULA(x) ((x / 2) / 4) - 1 + +/* Define Display OFFSET */ +/* VT3314 chipset */ +#define CN700_IGA1_FIFO_MAX_DEPTH 96 /* location: {SR17,0,7}*/ +#define CN700_IGA1_FIFO_THRESHOLD 80 /* location: {SR16,0,5},{SR16,7,7}*/ +#define CN700_IGA1_FIFO_HIGH_THRESHOLD 64 /* location: {SR18,0,5},{SR18,7,7}*/ +#define CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 0 /* location: {SR22,0,4}. (128/4) =64, + * P800 must be set zero, because HW + * only 5 bits */ +#define CN700_IGA2_FIFO_MAX_DEPTH 96 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7}*/ +#define CN700_IGA2_FIFO_THRESHOLD 80 /* location: {CR68,0,3},{CR95,4,6}*/ +#define CN700_IGA2_FIFO_HIGH_THRESHOLD 32 /* location: {CR92,0,3},{CR95,0,2}*/ +#define CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 /* location: {CR94,0,6}*/ + +/* For VT3324, these values are suggested by HW */ +#define CX700_IGA1_FIFO_MAX_DEPTH 192 /* location: {SR17,0,7}*/ +#define CX700_IGA1_FIFO_THRESHOLD 128 /* location: {SR16,0,5},{SR16,7,7}*/ +#define CX700_IGA1_FIFO_HIGH_THRESHOLD 128 /* location: {SR18,0,5},{SR18,7,7} */ +#define CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 /* location: {SR22,0,4} */ + +#define CX700_IGA2_FIFO_MAX_DEPTH 96 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7}*/ +#define CX700_IGA2_FIFO_THRESHOLD 64 /* location: {CR68,0,3},{CR95,4,6}*/ +#define CX700_IGA2_FIFO_HIGH_THRESHOLD 32 /* location: {CR92,0,3},{CR95,0,2} */ +#define CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 /* location: {CR94,0,6}*/ + +/* VT3336 chipset */ +#define K8M890_IGA1_FIFO_MAX_DEPTH 360 /* location: {SR17,0,7}*/ +#define K8M890_IGA1_FIFO_THRESHOLD 328 /* location: {SR16,0,5},{SR16,7,7}*/ +#define K8M890_IGA1_FIFO_HIGH_THRESHOLD 296 /* location: {SR18,0,5},{SR18,7,7}*/ +#define K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 124 /* location: {SR22,0,4}.*/ + +#define K8M890_IGA2_FIFO_MAX_DEPTH 360 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7}*/ +#define K8M890_IGA2_FIFO_THRESHOLD 328 /* location: {CR68,0,3},{CR95,4,6}*/ +#define K8M890_IGA2_FIFO_HIGH_THRESHOLD 296 /* location: {CR92,0,3},{CR95,0,2}*/ +#define K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 124 /* location: {CR94,0,6}*/ + +/* VT3327 chipset */ +#define P4M890_IGA1_FIFO_MAX_DEPTH 96 /* location: {SR17,0,7}*/ +#define P4M890_IGA1_FIFO_THRESHOLD 76 /* location: {SR16,0,5},{SR16,7,7}*/ +#define P4M890_IGA1_FIFO_HIGH_THRESHOLD 64 /* location: {SR18,0,5},{SR18,7,7}*/ +#define P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 /* location: {SR22,0,4}. (32/4) =8*/ + +#define P4M890_IGA2_FIFO_MAX_DEPTH 96 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7}*/ +#define P4M890_IGA2_FIFO_THRESHOLD 76 /* location: {CR68,0,3},{CR95,4,6}*/ +#define P4M890_IGA2_FIFO_HIGH_THRESHOLD 64 /* location: {CR92,0,3},{CR95,0,2}*/ +#define P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 /* location: {CR94,0,6}*/ + +/* VT3364 chipset */ +#define P4M900_IGA1_FIFO_MAX_DEPTH 96 /* location: {SR17,0,7}*/ +#define P4M900_IGA1_FIFO_THRESHOLD 76 /* location: {SR16,0,5},{SR16,7,7}*/ +#define P4M900_IGA1_FIFO_HIGH_THRESHOLD 76 /* location: {SR18,0,5},{SR18,7,7}*/ +#define P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 /* location: {SR22,0,4}.*/ + +#define P4M900_IGA2_FIFO_MAX_DEPTH 96 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7}*/ +#define P4M900_IGA2_FIFO_THRESHOLD 76 /* location: {CR68,0,3},{CR95,4,6}*/ +#define P4M900_IGA2_FIFO_HIGH_THRESHOLD 76 /* location: {CR92,0,3},{CR95,0,2}*/ +#define P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 /* location: {CR94,0,6}*/ + +/* For VT3353, these values are suggested by HW */ +#define VX800_IGA1_FIFO_MAX_DEPTH 192 /* location: {SR17,0,7}*/ +#define VX800_IGA1_FIFO_THRESHOLD 152 /* location: {SR16,0,5},{SR16,7,7}*/ +#define VX800_IGA1_FIFO_HIGH_THRESHOLD 152 /* location: {SR18,0,5},{SR18,7,7} */ +#define VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 64 /* location: {SR22,0,4} */ + +#define VX800_IGA2_FIFO_MAX_DEPTH 96 /* location: {CR68,4,7},{CR94,7,7},{CR95,7,7}*/ +#define VX800_IGA2_FIFO_THRESHOLD 64 /* location: {CR68,0,3},{CR95,4,6}*/ +#define VX800_IGA2_FIFO_HIGH_THRESHOLD 32 /* location: {CR92,0,3},{CR95,0,2} */ +#define VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 128 /* location: {CR94,0,6}*/ + +/* For VT3409 */ +#define VX855_IGA1_FIFO_MAX_DEPTH 400 +#define VX855_IGA1_FIFO_THRESHOLD 320 +#define VX855_IGA1_FIFO_HIGH_THRESHOLD 320 +#define VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160 + +#define VX855_IGA2_FIFO_MAX_DEPTH 200 +#define VX855_IGA2_FIFO_THRESHOLD 160 +#define VX855_IGA2_FIFO_HIGH_THRESHOLD 160 +#define VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320 + +/* For VT3410 */ +#define VX900_IGA1_FIFO_MAX_DEPTH 400 +#define VX900_IGA1_FIFO_THRESHOLD 320 +#define VX900_IGA1_FIFO_HIGH_THRESHOLD 320 +#define VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 160 + +#define VX900_IGA2_FIFO_MAX_DEPTH 192 +#define VX900_IGA2_FIFO_THRESHOLD 160 +#define VX900_IGA2_FIFO_HIGH_THRESHOLD 160 +#define VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 320 + +#ifdef VIA_VT3293_SUPPORT +/* For VT3293 */ +#define CN750_IGA1_FIFO_MAX_DEPTH 96 +#define CN750_IGA1_FIFO_THRESHOLD 76 +#define CN750_IGA1_FIFO_HIGH_THRESHOLD 76 +#define CN750_IGA1_DISPLAY_QUEUE_EXPIRE_NUM 32 + +#define CN750_IGA2_FIFO_MAX_DEPTH 96 +#define CN750_IGA2_FIFO_THRESHOLD 76 +#define CN750_IGA2_FIFO_HIGH_THRESHOLD 76 +#define CN750_IGA2_DISPLAY_QUEUE_EXPIRE_NUM 32 +#endif + +/* IGA1 FIFO Depth_Select */ +static struct vga_regset iga1_fifo_depth_select[] = { + { VGA_SEQ_I, 0x17, 0, 7 } +}; + +/* IGA2 FIFO Depth_Select */ +static struct vga_regset iga2_fifo_depth_select[] = { + { VGA_CRT_IC, 0x68, 4, 7 }, + { VGA_CRT_IC, 0x94, 7, 7 }, + { VGA_CRT_IC, 0x95, 7, 7 } +}; + +/* IGA1 FIFO Threshold Select */ +static struct vga_regset iga1_fifo_threshold_select[] = { + { VGA_SEQ_I, 0x16, 0, 5 }, + { VGA_SEQ_I, 0x16, 7, 7 } +}; + +/* IGA2 FIFO Threshold Select */ +static struct vga_regset iga2_fifo_threshold_select[] = { + { VGA_CRT_IC, 0x68, 0, 3 }, + { VGA_CRT_IC, 0x95, 4, 6 } +}; + +/* IGA1 FIFO High Threshold Select */ +static struct vga_regset iga1_fifo_high_threshold_select[] = { + { VGA_SEQ_I, 0x18, 0, 5 }, + { VGA_SEQ_I, 0x18, 7, 7 } +}; + +/* IGA2 FIFO High Threshold Select */ +static struct vga_regset iga2_fifo_high_threshold_select[] = { + { VGA_CRT_IC, 0x92, 0, 3 }, + { VGA_CRT_IC, 0x95, 0, 2 } +}; + +/* IGA1 FIFO display queue expire */ +static struct vga_regset iga1_display_queue_expire_num[] = { + { VGA_SEQ_I, 0x22, 0, 4 }, + { VGA_SEQ_I, 0x57, 6, 6 } +}; + +/* IGA2 FIFO display queue expire */ +static struct vga_regset iga2_display_queue_expire_num[] = { + { VGA_CRT_IC, 0x94, 0, 6 } +}; + +/***********************************************/ +/************* Offset register *****************/ +/***********************************************/ + +/* IGA1 Offset Register */ +static struct vga_regset iga1_offset[] = { + { VGA_CRT_IC, 0x13, 0, 7 }, + { VGA_CRT_IC, 0x35, 5, 7 } +}; + +/* IGA2 Offset Register */ +static struct vga_regset iga2_offset[] = { + { VGA_CRT_IC, 0x66, 0, 7 }, + { VGA_CRT_IC, 0x67, 0, 1 }, + { VGA_CRT_IC, 0x71, 7, 7 } +}; + +/***********************************************/ +/*********** Fetch count register **************/ +/***********************************************/ + +/* IGA1 Fetch Count Register */ +static struct vga_regset iga1_fetch_count[] = { + { VGA_SEQ_I, 0x1C, 0, 7 }, + { VGA_SEQ_I, 0x1D, 0, 1 } +}; + +/* IGA2 Fetch Count Register */ +static struct vga_regset iga2_fetch_count[] = { + { VGA_CRT_IC, 0x65, 0, 7 }, + { VGA_CRT_IC, 0x67, 2, 3 } +}; + +/************************************************/ +/*********** IGA Scaling Factor Registers *******/ +/************************************************/ +#define LCD_HOR_SCALE_FACTOR_FORMULA(x, y) (((x - 1) * 4096) / (y - 1)) +#define LCD_VER_SCALE_FACTOR_FORMULA(x, y) (((x - 1) * 2048) / (y - 1)) + +static struct vga_regset lcd_hor_scaling[] = { + { VGA_CRT_IC, 0x9F, 0, 1 }, + { VGA_CRT_IC, 0x77, 0, 7 }, + { VGA_CRT_IC, 0x79, 4, 5 } +}; + +static struct vga_regset lcd_ver_scaling[] = { + { VGA_CRT_IC, 0x79, 3, 3 }, + { VGA_CRT_IC, 0x78, 0, 7 }, + { VGA_CRT_IC, 0x79, 6, 7 } +}; + +/***********************************************/ +/*********** CRTC timing register **************/ +/***********************************************/ + +/***************************************************/ +/* Definition IGA1 Design Method of CRTC Registers */ +/***************************************************/ +#define IGA1_HOR_TOTAL_FORMULA(x) (x / 8) - 5 +#define IGA1_HOR_ADDR_FORMULA(x) (x / 8) - 1 +#define IGA1_HOR_BLANK_START_FORMULA(x) (x / 8) - 1 +#define IGA1_HOR_BLANK_END_FORMULA(x) (x / 8) - 1 +#define IGA1_HOR_SYNC_START_FORMULA(x) (x / 8) - 1 +#define IGA1_HOR_SYNC_END_FORMULA(x) (x / 8) - 1 + +#define IGA1_VER_TOTAL_FORMULA(x) (x - 2) +#define IGA1_VER_ADDR_FORMULA(x) (x - 1) +#define IGA1_VER_BLANK_START_FORMULA(x) (x - 1) +#define IGA1_VER_BLANK_END_FORMULA(x) (x - 1) +#define IGA1_VER_SYNC_START_FORMULA(x) (x - 1) +#define IGA1_VER_SYNC_END_FORMULA(x) (x - 1) + +/***************************************************/ +/* Definition IGA2 Design Method of CRTC Registers */ +/***************************************************/ +#define IGA2_HOR_TOTAL_FORMULA(x) (x - 1) +#define IGA2_HOR_ADDR_FORMULA(x) (x - 1) +#define IGA2_HOR_BLANK_START_FORMULA(x) (x - 1) +#define IGA2_HOR_BLANK_END_FORMULA(x) (x - 1) +#define IGA2_HOR_SYNC_START_FORMULA(x) (x - 1) +#define IGA2_HOR_SYNC_END_FORMULA(x) (x - 1) + +#define IGA2_VER_TOTAL_FORMULA(x) (x - 1) +#define IGA2_VER_ADDR_FORMULA(x) (x - 1) +#define IGA2_VER_BLANK_START_FORMULA(x) (x - 1) +#define IGA2_VER_BLANK_END_FORMULA(x) (x - 1) +#define IGA2_VER_SYNC_START_FORMULA(x) (x - 1) +#define IGA2_VER_SYNC_END_FORMULA(x) (x - 1) + +/****************************************************************/ +/* Definition IGA1 Design Method of CRTC Pixel timing Registers */ +/****************************************************************/ +#define IGA1_PIXELTIMING_HOR_TOTAL_FORMULA(x) (x - 1) +#define IGA1_PIXELTIMING_HOR_ADDR_FORMULA(x) (x - 1) +#define IGA1_PIXELTIMING_HOR_BLANK_START_FORMULA(x) (x - 1) +#define IGA1_PIXELTIMING_HOR_BLANK_END_FORMULA(x) (x - 1) +#define IGA1_PIXELTIMING_HOR_SYNC_START_FORMULA(x) (x - 1) +#define IGA1_PIXELTIMING_HOR_SYNC_END_FORMULA(x) (x - 1) + +#define IGA1_PIXELTIMING_VER_TOTAL_FORMULA(x) (x - 2) +#define IGA1_PIXELTIMING_VER_ADDR_FORMULA(x) (x - 1) +#define IGA1_PIXELTIMING_VER_BLANK_START_FORMULA(x) (x - 1) +#define IGA1_PIXELTIMING_VER_BLANK_END_FORMULA(x) (x - 1) +#define IGA1_PIXELTIMING_VER_SYNC_START_FORMULA(x) (x - 1) +#define IGA1_PIXELTIMING_VER_SYNC_END_FORMULA(x) (x - 1) + +#define IGA1_PIXELTIMING_HVSYNC_OFFSET_END_FORMULA(x, y) \ + ((x / 2) - 1 - (x - y)) + +/************************************************/ +/* Define IGA1 Display Timing */ +/************************************************/ + +/* IGA1 Horizontal Total */ +static struct vga_regset iga1_hor_total[] = { + { VGA_CRT_IC, 0x00, 0, 7 }, + { VGA_CRT_IC, 0x36, 3, 3 } +}; + +/* IGA1 Horizontal Addressable Video */ +static struct vga_regset iga1_hor_addr[] = { + { VGA_CRT_IC, 0x01, 0, 7 }, + { VGA_CRT_IC, 0x45, 1, 1 } +}; + +/* IGA1 Horizontal Blank Start */ +static struct vga_regset iga1_hor_blank_start[] = { + { VGA_CRT_IC, 0x02, 0, 7 }, + { VGA_CRT_IC, 0x45, 2, 2 } +}; + +/* IGA1 Horizontal Blank End */ +static struct vga_regset iga1_hor_blank_end[] = { + { VGA_CRT_IC, 0x03, 0, 4 }, + { VGA_CRT_IC, 0x05, 7, 7 }, + { VGA_CRT_IC, 0x33, 5, 5 } +}; + +/* IGA1 Horizontal Sync Start */ +static struct vga_regset iga1_hor_sync_start[] = { + { VGA_CRT_IC, 0x04, 0, 7 }, + { VGA_CRT_IC, 0x33, 4, 4 } +}; + +/* IGA1 Horizontal Sync End */ +static struct vga_regset iga1_hor_sync_end[] = { + { VGA_CRT_IC, 0x05, 0, 4 } +}; + +/* IGA1 Vertical Total */ +static struct vga_regset iga1_ver_total[] = { + { VGA_CRT_IC, 0x06, 0, 7 }, + { VGA_CRT_IC, 0x07, 0, 0 }, + { VGA_CRT_IC, 0x07, 5, 5 }, + { VGA_CRT_IC, 0x35, 0, 0 } +}; + +/* IGA1 Vertical Addressable Video */ +static struct vga_regset iga1_ver_addr[] = { + { VGA_CRT_IC, 0x12, 0, 7 }, + { VGA_CRT_IC, 0x07, 1, 1 }, + { VGA_CRT_IC, 0x07, 6, 6 }, + { VGA_CRT_IC, 0x35, 2, 2 } +}; + +/* IGA1 Vertical Blank Start */ +static struct vga_regset iga1_ver_blank_start[] = { + { VGA_CRT_IC, 0x15, 0, 7 }, + { VGA_CRT_IC, 0x07, 3, 3 }, + { VGA_CRT_IC, 0x09, 5, 5 }, + { VGA_CRT_IC, 0x35, 3, 3 } +}; + +/* IGA1 Vertical Blank End */ +static struct vga_regset iga1_ver_blank_end[] = { + { VGA_CRT_IC, 0x16, 0, 7 } +}; + +/* IGA1 Vertical Sync Start */ +static struct vga_regset iga1_ver_sync_start[] = { + { VGA_CRT_IC, 0x10, 0, 7 }, + { VGA_CRT_IC, 0x07, 2, 2 }, + { VGA_CRT_IC, 0x07, 7, 7 }, + { VGA_CRT_IC, 0x35, 1, 1 } +}; + +/* IGA1 Vertical Sync End */ +static struct vga_regset iga1_ver_sync_end[] = { + { VGA_CRT_IC, 0x11, 0, 3 } +}; + +/************************************************/ +/* Define IGA2 Display Timing */ +/************************************************/ + +/* IGA2 Horizontal Total */ +static struct vga_regset iga2_hor_total[] = { + { VGA_CRT_IC, 0x50, 0, 7 }, + { VGA_CRT_IC, 0x55, 0, 3 } +}; + +/* IGA2 Horizontal Addressable Video */ +static struct vga_regset iga2_hor_addr[] = { + { VGA_CRT_IC, 0x51, 0, 7 }, + { VGA_CRT_IC, 0x55, 4, 6 }, + { VGA_CRT_IC, 0x55, 7, 7 } +}; + +/* IGA2 Horizontal Blank Start */ +static struct vga_regset iga2_hor_blank_start[] = { + { VGA_CRT_IC, 0x52, 0, 7 }, + { VGA_CRT_IC, 0x54, 0, 2 }, + { VGA_CRT_IC, 0x6B, 0, 0 } +}; + +/* IGA2 Horizontal Blank End */ +static struct vga_regset iga2_hor_blank_end[] = { + { VGA_CRT_IC, 0x53, 0, 7 }, + { VGA_CRT_IC, 0x54, 3, 5 }, + { VGA_CRT_IC, 0x5D, 6, 6 } +}; + +/* IGA2 Horizontal Sync Start */ +static struct vga_regset iga2_hor_sync_start[] = { + { VGA_CRT_IC, 0x56, 0, 7 }, + { VGA_CRT_IC, 0x54, 6, 7 }, + { VGA_CRT_IC, 0x5C, 7, 7 }, + { VGA_CRT_IC, 0x5D, 7, 7 } +}; + +/* IGA2 Horizontal Sync End */ +static struct vga_regset iga2_hor_sync_end[] = { + { VGA_CRT_IC, 0x57, 0, 7 }, + { VGA_CRT_IC, 0x5C, 6, 6 } +}; + +/* IGA2 Vertical Total */ +static struct vga_regset iga2_ver_total[] = { + { VGA_CRT_IC, 0x58, 0, 7 }, + { VGA_CRT_IC, 0x5D, 0, 2 } +}; + +/* IGA2 Vertical Addressable Video */ +static struct vga_regset iga2_ver_addr[] = { + { VGA_CRT_IC, 0x59, 0, 7 }, + { VGA_CRT_IC, 0x5D, 3, 5 } +}; + +/* IGA2 Vertical Blank Start */ +static struct vga_regset iga2_ver_blank_start[] = { + { VGA_CRT_IC, 0x5A, 0, 7 }, + { VGA_CRT_IC, 0x5C, 0, 2 } +}; + +/* IGA2 Vertical Blank End */ +static struct vga_regset iga2_ver_blank_end[] = { + { VGA_CRT_IC, 0x5B, 0, 7 }, + { VGA_CRT_IC, 0x5C, 3, 5 } +}; + +/* IGA2 Vertical Sync Start */ +static struct vga_regset iga2_ver_sync_start[] = { + { VGA_CRT_IC, 0x5E, 0, 7 }, + { VGA_CRT_IC, 0x5F, 5, 7 } +}; + +/* IGA2 Vertical Sync End */ +static struct vga_regset iga2_ver_sync_end[] = { + { VGA_CRT_IC, 0x5F, 0, 4 } +}; + +/* IGA1 pixel timing Registers */ +#define IGA1_PIX_H_TOTAL_REG 0x8400 //[15:0] +#define IGA1_PIX_H_ADDR_REG 0x8400 //[31:16] +#define IGA1_PIX_H_BNK_ST_REG 0x8404 //[15:0] +#define IGA1_PIX_H_BNK_END_REG 0x8404 //[31:16] +#define IGA1_PIX_H_SYNC_ST_REG 0x8408 //[15:0] +#define IGA1_PIX_H_SYNC_END_REG 0x8408 //[31:16] +#define IGA1_PIX_V_TOTAL_REG 0x8424 //[10:0] +#define IGA1_PIX_V_ADDR_REG 0x8424 //[26:16] +#define IGA1_PIX_V_BNK_ST_REG 0x8428 //[10:0] +#define IGA1_PIX_V_BNK_END_REG 0x8428 //[26:16] +#define IGA1_PIX_V_SYNC_ST_REG 0x842C //[10:0] +#define IGA1_PIX_V_SYNC_END_REG 0x842C //[15:12] +#define IGA1_PIX_HALF_LINE_REG 0x8434 //[15:0] + +#define IGA1_PIX_H_TOTAL_MASK 0x0000FFFF //[15:0] +#define IGA1_PIX_H_ADDR_MASK 0xFFFF0000 //[31:16] +#define IGA1_PIX_H_BNK_ST_MASK 0x0000FFFF //[15:0] +#define IGA1_PIX_H_BNK_END_MASK 0xFFFF0000 //[31:16] +#define IGA1_PIX_H_SYNC_ST_MASK 0x0000FFFF //[15:0] +#define IGA1_PIX_H_SYNC_END_MASK 0xFFFF0000 //[31:16] +#define IGA1_PIX_V_TOTAL_MASK 0x000007FF //[10:0] +#define IGA1_PIX_V_ADDR_MASK 0x07FF0000 //[26:16] +#define IGA1_PIX_V_BNK_ST_MASK 0x000007FF //[10:0] +#define IGA1_PIX_V_BNK_END_MASK 0x07FF0000 //[26:16] +#define IGA1_PIX_V_SYNC_ST_MASK 0x000007FF //[10:0] +#define IGA1_PIX_V_SYNC_END_MASK 0x0000F000 //[15:12] +#define IGA1_PIX_HALF_LINE_MASK 0x0000FFFF //[15:0] + +#endif diff --git a/drivers/gpu/drm/via/via_regs.h b/drivers/gpu/drm/via/via_regs.h new file mode 100644 index 0000000..ae74eb7 --- /dev/null +++ b/drivers/gpu/drm/via/via_regs.h @@ -0,0 +1,297 @@ +/* + * Copyright 2012 James Simmons jsimmons@infradead.org + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + */ + +/************************************************************************* + * + * File: via_regs.h + * Content: The defines of Via registers + * + ************************************************************************/ + +#ifndef _VIA_REGS_H_ +#define _VIA_REGS_H_ 1 + +#define BIOS_BSIZE 1024 +#define BIOS_BASE 0xc0000 + +#define VIA_MMIO_REGSIZE 0xD000 /* DisplayPort:0xC610~0xC7D4 */ +#define VIA_MMIO_REGBASE 0x0 +#define VIA_MMIO_VGABASE 0x8000 +#define VIA_MMIO_BLTBASE 0x200000 +#define VIA_MMIO_BLTSIZE 0x200000 + +/* defines for VIA 2D registers */ +#define VIA_REG_GECMD 0x000 +#define VIA_REG_GEMODE 0x004 +#define VIA_REG_GESTATUS 0x004 /* as same as VIA_REG_GEMODE */ +#define VIA_REG_SRCPOS 0x008 +#define VIA_REG_DSTPOS 0x00C +#define VIA_REG_LINE_K1K2 0x008 +#define VIA_REG_LINE_XY 0x00C +#define VIA_REG_DIMENSION 0x010 /* width and height */ +#define VIA_REG_PATADDR 0x014 +#define VIA_REG_FGCOLOR 0x018 +#define VIA_REG_DSTCOLORKEY 0x018 /* as same as VIA_REG_FG */ +#define VIA_REG_BGCOLOR 0x01C +#define VIA_REG_SRCCOLORKEY 0x01C /* as same as VIA_REG_BG */ +#define VIA_REG_CLIPTL 0x020 /* top and left of clipping */ +#define VIA_REG_CLIPBR 0x024 /* bottom and right of clipping */ +#define VIA_REG_OFFSET 0x028 +#define VIA_REG_LINE_ERROR 0x028 +#define VIA_REG_KEYCONTROL 0x02C /* color key control */ +#define VIA_REG_SRCBASE 0x030 +#define VIA_REG_DSTBASE 0x034 +#define VIA_REG_PITCH 0x038 /* pitch of src and dst */ +#define VIA_REG_MONOPAT0 0x03C +#define VIA_REG_MONOPAT1 0x040 +#define VIA_REG_COLORPAT 0x100 /* from 0x100 to 0x1ff */ + +/* defineds vor VIA 2D registers for VT3353 (M1 engine) */ +#define VIA_REG_GECMD_M1 0x000 +#define VIA_REG_GEMODE_M1 0x004 +#define VIA_REG_GESTATUS_M1 0x004 /* as same as VIA_REG_GEMODE */ +#define VIA_REG_PITCH_M1 0x008 /* pitch of src and dst */ +#define VIA_REG_DIMENSION_M1 0x00C /* width and height */ +#define VIA_REG_DSTPOS_M1 0x010 +#define VIA_REG_LINE_XY_M1 0x010 +#define VIA_REG_DSTBASE_M1 0x014 +#define VIA_REG_SRCPOS_M1 0x018 +#define VIA_REG_LINE_K1K2_M1 0x018 +#define VIA_REG_SRCBASE_M1 0x01C +#define VIA_REG_PATADDR_M1 0x020 +#define VIA_REG_MONOPAT0_M1 0x024 +#define VIA_REG_MONOPAT1_M1 0x028 +#define VIA_REG_OFFSET_M1 0x02C +#define VIA_REG_LINE_ERROR_M1 0x02C +#define VIA_REG_CLIPTL_M1 0x040 /* top and left of clipping */ +#define VIA_REG_CLIPBR_M1 0x044 /* bottom and right of clipping */ +#define VIA_REG_KEYCONTROL_M1 0x048 /* color key control */ +#define VIA_REG_FGCOLOR_M1 0x04C +#define VIA_REG_DSTCOLORKEY_M1 0x04C /* as same as VIA_REG_FG */ +#define VIA_REG_BGCOLOR_M1 0x050 +#define VIA_REG_SRCCOLORKEY_M1 0x050 /* as same as VIA_REG_BG */ +#define VIA_REG_MONOPATFGC_M1 0x058 /* Add foreground color of Pattern */ +#define VIA_REG_MONOPATBGC_M1 0x05C /* Add background color of Pattern */ +#define VIA_REG_COLORPAT_M1 0x100 /* from 0x100 to 0x1ff */ + +/* defines for VIA video registers */ +#define VIA_REG_INTERRUPT 0x200 +#define VIA_REG_CRTCSTART 0x214 + +/*CN400 and older Hardware Icon engine register*/ +#define HI_POSSTART 0x208 +#define HI_CENTEROFFSET 0x20C +#define HI_FBOFFSET 0x224 +#define HI_CONTROL 0x260 +#define HI_TRANSPARENT_COLOR 0x270 +#define HI_INVTCOLOR 0x274 +/* VT3324 primary Hardware Icon engine register */ +#define PRIM_HI_POSEND 0x290 +#define V327_HI_INVTCOLOR 0x2E4 +#define PRIM_HI_FIFO 0x2E8 +#define PRIM_HI_TRANSCOLOR 0x2EC +#define PRIM_HI_CTRL 0x2F0 +#define PRIM_HI_FBOFFSET 0x2F4 +#define PRIM_HI_POSSTART 0x2F8 +#define PRIM_HI_CENTEROFFSET 0x2FC +#define PRIM_HI_INVTCOLOR 0x120C + +#define ALPHA_V3_PREFIFO_CONTROL 0x268 +#define ALPHA_V3_FIFO_CONTROL 0x278 + +/* defines for VIA 3D registers */ +#define VIA_REG_STATUS 0x400 +#define VIA_REG_TRANSET 0x43C +#define VIA_REG_TRANSPACE 0x440 + +/* VIA_REG_STATUS(0x400): Engine Status */ +#define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ +#define VIA_2D_ENG_BUSY 0x00000002 /* 2D Engine is busy */ +#define VIA_3D_ENG_BUSY 0x00000001 /* 3D Engine is busy */ +#define VIA_VR_QUEUE_EMPTY 0x00020000 /* Virtual Queue is busy */ + +/* VIA_REG_STATUS(0x400): Egine Status */ +#define VIA_CMD_RGTR_BUSY_H5 0x00000010 /* Command Regulator is busy */ +#define VIA_2D_ENG_BUSY_H5 0x00000002 /* 2D Engine is busy */ +#define VIA_3D_ENG_BUSY_H5 0x00001FE1 /* 3D Engine is busy */ +#define VIA_VR_QUEUE_BUSY_H5 0x00000004 /* Virtual Queue is busy */ + +/* VIA_REG_GECMD(0x00): 2D Engine Command */ +#define VIA_GEC_NOOP 0x00000000 +#define VIA_GEC_BLT 0x00000001 +#define VIA_GEC_LINE 0x00000005 + +#define VIA_GEC_SRC_XY 0x00000000 +#define VIA_GEC_SRC_LINEAR 0x00000010 +#define VIA_GEC_DST_XY 0x00000000 +#define VIA_GEC_DST_LINRAT 0x00000020 + +#define VIA_GEC_SRC_FB 0x00000000 +#define VIA_GEC_SRC_SYS 0x00000040 +#define VIA_GEC_DST_FB 0x00000000 +#define VIA_GEC_DST_SYS 0x00000080 + +#define VIA_GEC_SRC_MONO 0x00000100 /* source is mono */ +#define VIA_GEC_PAT_MONO 0x00000200 /* pattern is mono */ + +#define VIA_GEC_MSRC_OPAQUE 0x00000000 /* mono src is opaque */ +#define VIA_GEC_MSRC_TRANS 0x00000400 /* mono src is transparent */ + +#define VIA_GEC_PAT_FB 0x00000000 /* pattern is in frame buffer */ +#define VIA_GEC_PAT_REG 0x00000800 /* pattern is from reg setting */ + +#define VIA_GEC_CLIP_DISABLE 0x00000000 +#define VIA_GEC_CLIP_ENABLE 0x00001000 + +#define VIA_GEC_FIXCOLOR_PAT 0x00002000 + +#define VIA_GEC_INCX 0x00000000 +#define VIA_GEC_DECY 0x00004000 +#define VIA_GEC_INCY 0x00000000 +#define VIA_GEC_DECX 0x00008000 + +#define VIA_GEC_MPAT_OPAQUE 0x00000000 /* mono pattern is opaque */ +#define VIA_GEC_MPAT_TRANS 0x00010000 /* mono pattern is transparent */ + +#define VIA_GEC_MONO_UNPACK 0x00000000 +#define VIA_GEC_MONO_PACK 0x00020000 +#define VIA_GEC_MONO_DWORD 0x00000000 +#define VIA_GEC_MONO_WORD 0x00040000 +#define VIA_GEC_MONO_BYTE 0x00080000 + +#define VIA_GEC_LASTPIXEL_ON 0x00000000 +#define VIA_GEC_LASTPIXEL_OFF 0x00100000 +#define VIA_GEC_X_MAJOR 0x00000000 +#define VIA_GEC_Y_MAJOR 0x00200000 +#define VIA_GEC_QUICK_START 0x00800000 + + +/* VIA_REG_GEMODE(0x04): GE mode */ +#define VIA_GEM_8bpp 0x00000000 +#define VIA_GEM_16bpp 0x00000100 +#define VIA_GEM_32bpp 0x00000300 + +#define VIA_GEM_640 0x00000000 /* 640*480 */ +#define VIA_GEM_800 0x00000400 /* 800*600 */ +#define VIA_GEM_1024 0x00000800 /* 1024*768 */ +#define VIA_GEM_1280 0x00000C00 /* 1280*1024 */ +#define VIA_GEM_1600 0x00001000 /* 1600*1200 */ +#define VIA_GEM_2048 0x00001400 /* 2048*1536 */ + +/* VIA_REG_PITCH(0x38): Pitch Setting */ +#define VIA_PITCH_ENABLE 0x80000000 + +/* CN400 HQV offset */ +#define REG_HQV1_INDEX 0x00001000 + +/************************************************ + * DisplayPort Register + ************************************************/ +#define DP_DATA_PASS_ENABLE_REG 0xC000 + +#define DP_ATTR_DATA_REG 0xC610 +#define DP_LINK_TRAINING_REG 0xC614 +#define DP_VIDEO_CTRL_REG 0xC618 +#define DP_VER_EXT_PKT_HEAD_REG 0xC61C + +/* DP Display Port Enable and InfoFrame Control */ +#define DP_ENABLE_IF_REG 0xC640 +#define DP_HWIDTH_TUSIZE_REG 0xC644 +#define DP_HLINE_DUR_REG 0xC648 +#define DP_MVID_MISC0_REG 0xC64C + +#define DP_H_ATTR_REG 0xC650 +#define DP_HV_START_REG 0xC654 +#define DP_POLARITY_WIDTH_REG 0xC658 +#define DP_ACITVE_WH_REG 0xC65C + +#define AUX_W_DATA0_REG 0xC710 +#define AUX_W_DATA1_REG 0xC714 +#define AUX_W_DATA2_REG 0xC718 +#define AUX_W_DATA3_REG 0xC71C + +#define AUX_R_DATA0_REG 0xC720 +#define AUX_R_DATA1_REG 0xC724 +#define AUX_R_DATA2_REG 0xC728 +#define AUX_R_DATA3_REG 0xC72C +#define VIA_IRQ_DP_HOT_IRQ 0xC0000000 +#define VIA_IRQ_DP_HOT_UNPLUG 0x80000000 +#define VIA_IRQ_DP_HOT_PLUG 0x40000000 +#define VIA_IRQ_DP_NO_INT 0x00000000 + +#define AUX_TIMER_REG 0xC730 +#define AUX_CMD_REG 0xC734 +#define DP_NAUD_MUTE_REG 0xC738 + +#define DP_EPHY_PLL_REG 0xC740 +#define DP_EPHY_TX_PWR_REG 0xC744 +#define DP_EPHY_MISC_PWR_REG 0xC748 + +/************************************************* + * DisplayPort2 Register + *************************************************/ +#define DP2_NVID_MISC0_REG 0xC690 +#define DP2_LINK_TRAINING_REG 0xC694 +#define DP2_VIDEO_CTRL_REG 0xC698 +#define DP2_EXT_REG 0xC69C +#define DP2_VER_EXT_PKT_HEAD_REG 0xC61C + +/* DP2 Display Port Enable and InfoFrame Control */ +#define DP2_ENABLE_IF_REG 0xC6C0 +#define DP2_HWIDTH_TUSIZE_REG 0xC6C4 +#define DP2_HLINE_DUR_REG 0xC6C8 +#define DP2_MVID_MISC0_REG 0xC6CC + +#define DP2_H_ATTR_REG 0xC6D0 +#define DP2_HV_START_REG 0xC6D4 +#define DP2_POLARITY_WIDTH_REG 0xC6D8 +#define DP2_ACITVE_WH_REG 0xC6DC + +/* the same with DP1 */ +#define DP2_EPHY_SSC_REG 0xC740 +/* the same with DP1 */ +#define DP2_EPHY_RT_REG 0xC744 + +#define DP2_AUX_W_DATA0_REG 0xC790 +#define DP2_AUX_W_DATA1_REG 0xC794 +#define DP2_AUX_W_DATA2_REG 0xC798 +#define DP2_AUX_W_DATA3_REG 0xC79C + +#define DP2_AUX_R_DATA0_REG 0xC7A0 +#define DP2_AUX_R_DATA1_REG 0xC7A4 +#define DP2_AUX_R_DATA2_REG 0xC7A8 +#define DP2_AUX_R_DATA3_REG 0xC7AC + +#define DP2_AUX_TIMER_REG 0xC7B0 +#define DP2_AUX_CMD_REG 0xC7B4 +#define DP2_NAUD_MUTE_REG 0xC7B8 + +#define DP2_EPHY_TX_PWR_REG2 0xC7C0 +#define DP2_EPHY_TX_IDLE_REG 0xC7C4 +#define DP2_EPHY_TX_PWR_REG 0xC7C8 +#define DP2_EPHY_PLL_REG 0xC7CC + +#endif /* _VIA_REGS_H_ */ diff --git a/drivers/gpu/drm/via/via_verifier.c b/drivers/gpu/drm/via/via_verifier.c index 9dbc92b..9e1da0d 100644 --- a/drivers/gpu/drm/via/via_verifier.c +++ b/drivers/gpu/drm/via/via_verifier.c @@ -27,23 +27,23 @@ * Don't run this code directly on an AGP buffer. Due to cache problems it will * be very slow. */ - -#include "via_3d_reg.h" #include <drm/drmP.h> #include <drm/via_drm.h> + +#include "via_3d_reg.h" #include "via_verifier.h" #include "via_drv.h"

-typedef enum { +enum verifier_state { state_command, state_header2, state_header1, state_vheader5, state_vheader6, state_error -} verifier_state_t; +};

-typedef enum { +enum hazard { no_check = 0, check_for_header2, check_for_header1, @@ -71,7 +71,7 @@ typedef enum { check_for_vertex_count, check_number_texunits, forbidden_command -} hazard_t; +};

/* * Associates each hazard above with a possible multi-command @@ -80,7 +80,7 @@ typedef enum { * that does not include any part of the address. */

-static drm_via_sequence_t seqs[] = { +static enum drm_via_sequence seqs[] = { no_sequence, no_sequence, no_sequence, @@ -108,12 +108,13 @@ static drm_via_sequence_t seqs[] = { no_sequence };

-typedef struct { +struct hz_init { unsigned int code; - hazard_t hz; -} hz_init_t; + enum hazard hz; +};

-static hz_init_t init_table1[] = { +/* for atrribute other than context hazard detect */ +static struct hz_init init_table1[] = { {0xf2, check_for_header2_err}, {0xf0, check_for_header1_err}, {0xee, check_for_fire}, @@ -164,7 +165,8 @@ static hz_init_t init_table1[] = { {0x7D, check_for_vertex_count} };

-static hz_init_t init_table2[] = { +/* for texture stage's hazard detect */ +static struct hz_init init_table2[] = { {0xf2, check_for_header2_err}, {0xf0, check_for_header1_err}, {0xee, check_for_fire}, @@ -179,6 +181,8 @@ static hz_init_t init_table2[] = { {0x07, check_texture_addr0}, {0x08, check_texture_addr0}, {0x09, check_texture_addr0}, + {0x0A, check_texture_addr0}, + {0x0B, check_texture_addr0}, {0x20, check_texture_addr1}, {0x21, check_texture_addr1}, {0x22, check_texture_addr1}, @@ -193,6 +197,8 @@ static hz_init_t init_table2[] = { {0x32, check_texture_addr3}, {0x33, check_texture_addr3}, {0x34, check_texture_addr3}, + {0x35, check_texture_addr3}, + {0x36, check_texture_addr3}, {0x4B, check_texture_addr5}, {0x4C, check_texture_addr6}, {0x51, check_texture_addr7}, @@ -222,16 +228,20 @@ static hz_init_t init_table2[] = { {0x93, no_check} };

-static hz_init_t init_table3[] = { +/* Check for flexible vertex format */ +static struct hz_init init_table3[] = { {0xf2, check_for_header2_err}, {0xf0, check_for_header1_err}, {0xcc, check_for_dummy}, - {0x00, check_number_texunits} + {0x00, check_number_texunits}, + {0x01, no_check}, + {0x02, no_check}, + {0x03, no_check} };

-static hazard_t table1[256]; -static hazard_t table2[256]; -static hazard_t table3[256]; +static enum hazard table1[256]; +static enum hazard table2[256]; +static enum hazard table3[256];

static __inline__ int eat_words(const uint32_t **buf, const uint32_t *buf_end, unsigned num_words) @@ -248,7 +258,7 @@ eat_words(const uint32_t **buf, const uint32_t *buf_end, unsigned num_words) * Partially stolen from drm_memory.h */

-static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t *seq, +static __inline__ drm_local_map_t *via_drm_lookup_agp_map(struct drm_via_state *seq, unsigned long offset, unsigned long size, struct drm_device *dev) @@ -285,7 +295,7 @@ static __inline__ drm_local_map_t *via_drm_lookup_agp_map(drm_via_state_t *seq, * very little CPU time. */

-static __inline__ int finish_current_sequence(drm_via_state_t * cur_seq) +static __inline__ int finish_current_sequence(struct drm_via_state * cur_seq) { switch (cur_seq->unfinished) { case z_address: @@ -343,7 +353,7 @@ static __inline__ int finish_current_sequence(drm_via_state_t * cur_seq) }

static __inline__ int -investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) +investigate_hazard(uint32_t cmd, enum hazard hz, struct drm_via_state *cur_seq) { register uint32_t tmp, *tmp_addr;

@@ -509,7 +519,7 @@ investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq) cur_seq->multitex = (cmd >> 3) & 1; return 0; default: - DRM_ERROR("Illegal DMA data: 0x%x\n", cmd); + DRM_ERROR("Illegal DMA data: 0x%08x\n", cmd); return 2; } return 2; @@ -517,10 +527,10 @@ investigate_hazard(uint32_t cmd, hazard_t hz, drm_via_state_t *cur_seq)

static __inline__ int via_check_prim_list(uint32_t const **buffer, const uint32_t * buf_end, - drm_via_state_t *cur_seq) + struct drm_via_state *cur_seq) { - drm_via_private_t *dev_priv = - (drm_via_private_t *) cur_seq->dev->dev_private; + struct drm_via_private *dev_priv = + (struct drm_via_private *) cur_seq->dev->dev_private; uint32_t a_fire, bcmd, dw_count; int ret = 0; int have_fire; @@ -619,15 +629,15 @@ via_check_prim_list(uint32_t const **buffer, const uint32_t * buf_end, return ret; }

-static __inline__ verifier_state_t +static __inline__ enum verifier_state via_check_header2(uint32_t const **buffer, const uint32_t *buf_end, - drm_via_state_t *hc_state) + struct drm_via_state *hc_state) { uint32_t cmd; int hz_mode; - hazard_t hz; + enum hazard hz; const uint32_t *buf = *buffer; - const hazard_t *hz_table; + const enum hazard *hz_table;

if ((buf_end - buf) < 2) { DRM_ERROR @@ -711,8 +721,8 @@ via_check_header2(uint32_t const **buffer, const uint32_t *buf_end, return state_command; }

-static __inline__ verifier_state_t -via_parse_header2(drm_via_private_t *dev_priv, uint32_t const **buffer, +static __inline__ enum verifier_state +via_parse_header2(struct drm_via_private *dev_priv, uint32_t const **buffer, const uint32_t *buf_end, int *fire_count) { uint32_t cmd; @@ -766,11 +776,12 @@ static __inline__ int verify_mmio_address(uint32_t address) DRM_ERROR("Invalid VIDEO DMA command. " "Attempt to access 3D- or command burst area.\n"); return 1; - } else if ((address > 0xCFF) && (address < 0x1300)) { + } else if ((address > 0xDFF) && (address < 0x1200)) { DRM_ERROR("Invalid VIDEO DMA command. " "Attempt to access PCI DMA area.\n"); return 1; - } else if (address > 0x13FF) { + } else if (((address > 0x13FF) && (address < 0x2200)) || + (address > 0x33ff)) { DRM_ERROR("Invalid VIDEO DMA command. " "Attempt to access VGA registers.\n"); return 1; @@ -778,6 +789,17 @@ static __inline__ int verify_mmio_address(uint32_t address) return 0; }

+static inline int is_dummy_cmd(uint32_t cmd) +{ + if ((cmd & INV_DUMMY_MASK) == 0xCC000000 || + (cmd & INV_DUMMY_MASK) == 0xCD000000 || + (cmd & INV_DUMMY_MASK) == 0xCE000000 || + (cmd & INV_DUMMY_MASK) == 0xCF000000 || + (cmd & INV_DUMMY_MASK) == 0xDD000000) + return 1; + return 0; +} + static __inline__ int verify_video_tail(uint32_t const **buffer, const uint32_t * buf_end, uint32_t dwords) @@ -789,21 +811,22 @@ verify_video_tail(uint32_t const **buffer, const uint32_t * buf_end, return 1; } while (dwords--) { - if (*buf++) { + if (*buf && !is_dummy_cmd(*buf)) { DRM_ERROR("Illegal video command tail.\n"); return 1; } + buf++; } *buffer = buf; return 0; }

-static __inline__ verifier_state_t +static __inline__ enum verifier_state via_check_header1(uint32_t const **buffer, const uint32_t * buf_end) { uint32_t cmd; const uint32_t *buf = *buffer; - verifier_state_t ret = state_command; + enum verifier_state ret = state_command;

while (buf < buf_end) { cmd = *buf; @@ -830,25 +853,36 @@ via_check_header1(uint32_t const **buffer, const uint32_t * buf_end) return ret; }

-static __inline__ verifier_state_t -via_parse_header1(drm_via_private_t *dev_priv, uint32_t const **buffer, +static __inline__ enum verifier_state +via_parse_header1(struct drm_via_private *dev_priv, uint32_t const **buffer, const uint32_t *buf_end) { - register uint32_t cmd; + register uint32_t cmd = VIA_REG_GECMD; const uint32_t *buf = *buffer;

while (buf < buf_end) { + + /* + * Wait idle to avoid lenghty PCI stalls. + * There is no on-chip queue for these MMIO commands, so + * without this idle wait, the chip will simply + * stall the PCI bus until the engines are idle. + */ + if (unlikely(cmd == VIA_REG_GECMD)) + via_wait_idle(dev_priv); + cmd = *buf; if ((cmd & HALCYON_HEADER1MASK) != HALCYON_HEADER1) break; - VIA_WRITE((cmd & ~HALCYON_HEADER1MASK) << 2, *++buf); + cmd = (cmd & ~HALCYON_HEADER1MASK) << 2; + VIA_WRITE(cmd, *++buf); buf++; } *buffer = buf; return state_command; }

-static __inline__ verifier_state_t +static __inline__ enum verifier_state via_check_vheader5(uint32_t const **buffer, const uint32_t *buf_end) { uint32_t data; @@ -881,8 +915,8 @@ via_check_vheader5(uint32_t const **buffer, const uint32_t *buf_end)

}

-static __inline__ verifier_state_t -via_parse_vheader5(drm_via_private_t *dev_priv, uint32_t const **buffer, +static __inline__ enum verifier_state +via_parse_vheader5(struct drm_via_private *dev_priv, uint32_t const **buffer, const uint32_t *buf_end) { uint32_t addr, count, i; @@ -899,7 +933,7 @@ via_parse_vheader5(drm_via_private_t *dev_priv, uint32_t const **buffer, return state_command; }

-static __inline__ verifier_state_t +static __inline__ enum verifier_state via_check_vheader6(uint32_t const **buffer, const uint32_t * buf_end) { uint32_t data; @@ -936,8 +970,8 @@ via_check_vheader6(uint32_t const **buffer, const uint32_t * buf_end) return state_command; }

-static __inline__ verifier_state_t -via_parse_vheader6(drm_via_private_t *dev_priv, uint32_t const **buffer, +static __inline__ enum verifier_state +via_parse_vheader6(struct drm_via_private *dev_priv, uint32_t const **buffer, const uint32_t *buf_end) {

@@ -962,19 +996,17 @@ via_verify_command_stream(const uint32_t * buf, unsigned int size, struct drm_device * dev, int agp) {

- drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; - drm_via_state_t *hc_state = &dev_priv->hc_state; - drm_via_state_t saved_state = *hc_state; + struct drm_via_private *dev_priv = dev->dev_private; + struct drm_via_state *hc_state = &dev_priv->hc_state; + struct drm_via_state saved_state = *hc_state; uint32_t cmd; const uint32_t *buf_end = buf + (size >> 2); - verifier_state_t state = state_command; + enum verifier_state state = state_command; int cme_video; int supported_3d;

- cme_video = (dev_priv->chipset == VIA_PRO_GROUP_A || - dev_priv->chipset == VIA_DX9_0); - - supported_3d = dev_priv->chipset != VIA_DX9_0; + cme_video = (dev_priv->engine_type != VIA_ENG_H1); + supported_3d = (dev_priv->engine_type < VIA_ENG_H5S1);

hc_state->dev = dev; hc_state->unfinished = no_sequence; @@ -1038,11 +1070,11 @@ via_parse_command_stream(struct drm_device *dev, const uint32_t *buf, unsigned int size) {

- drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; - uint32_t cmd; + struct drm_via_private *dev_priv = dev->dev_private; const uint32_t *buf_end = buf + (size >> 2); - verifier_state_t state = state_command; + enum verifier_state state = state_command; int fire_count = 0; + uint32_t cmd;

while (buf < buf_end) {

@@ -1088,7 +1120,7 @@ via_parse_command_stream(struct drm_device *dev, const uint32_t *buf, }

static void -setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size) +setup_hazard_table(struct hz_init init_table[], enum hazard table[], int size) { int i;

@@ -1102,9 +1134,9 @@ setup_hazard_table(hz_init_t init_table[], hazard_t table[], int size) void via_init_command_verifier(void) { setup_hazard_table(init_table1, table1, - sizeof(init_table1) / sizeof(hz_init_t)); + sizeof(init_table1) / sizeof(struct hz_init)); setup_hazard_table(init_table2, table2, - sizeof(init_table2) / sizeof(hz_init_t)); + sizeof(init_table2) / sizeof(struct hz_init)); setup_hazard_table(init_table3, table3, - sizeof(init_table3) / sizeof(hz_init_t)); + sizeof(init_table3) / sizeof(struct hz_init)); } diff --git a/drivers/gpu/drm/via/via_verifier.h b/drivers/gpu/drm/via/via_verifier.h index 26b6d36..906a61e 100644 --- a/drivers/gpu/drm/via/via_verifier.h +++ b/drivers/gpu/drm/via/via_verifier.h @@ -26,14 +26,16 @@ #ifndef _VIA_VERIFIER_H_ #define _VIA_VERIFIER_H_

-typedef enum { +#include "via_3d_reg.h" + +enum drm_via_sequence { no_sequence = 0, z_address, dest_address, tex_address -} drm_via_sequence_t; +};

-typedef struct { +struct drm_via_state { unsigned texture; uint32_t z_addr; uint32_t d_addr; @@ -44,7 +46,7 @@ typedef struct { uint32_t tex_level_hi[2]; uint32_t tex_palette_size[2]; uint32_t tex_npot[2]; - drm_via_sequence_t unfinished; + enum drm_via_sequence unfinished; int agp_texture; int multitex; struct drm_device *dev; @@ -52,11 +54,10 @@ typedef struct { uint32_t vertex_count; int agp; const uint32_t *buf_start; -} drm_via_state_t; +};

extern int via_verify_command_stream(const uint32_t *buf, unsigned int size, struct drm_device *dev, int agp); extern int via_parse_command_stream(struct drm_device *dev, const uint32_t *buf, unsigned int size); - #endif