On Wed, Sep 30, 2020 at 08:27:04PM -0400, Jonathan Marek wrote:
Add a new cache mode for creating coherent host-cached BOs.
Reviewed-by: Jordan Crouse jcrouse@codeaurora.org
Signed-off-by: Jonathan Marek jonathan@marek.ca
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/drm/msm/msm_drv.h | 1 + drivers/gpu/drm/msm/msm_gem.c | 8 ++++++++ include/uapi/drm/msm_drm.h | 5 ++--- 4 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 9eeb46bf2a5d..2aa707546254 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -410,6 +410,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid);
priv->is_a2xx = config.rev.core == 2;
priv->has_cached_coherent = config.rev.core >= 6;
gpu = info->init(drm); if (IS_ERR(gpu)) {
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 2c3225bc1794..6384844b1696 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -167,6 +167,7 @@ struct msm_drm_private { struct msm_file_private *lastctx; /* gpu is only set on open(), but we need this info earlier */ bool is_a2xx;
bool has_cached_coherent;
struct drm_fb_helper *fbdev;
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index b2f49152b4d4..ad9a627493ae 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -431,6 +431,9 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj, if (msm_obj->flags & MSM_BO_MAP_PRIV) prot |= IOMMU_PRIV;
if (msm_obj->flags & MSM_BO_CACHED_COHERENT)
prot |= IOMMU_CACHE;WARN_ON(!mutex_is_locked(&msm_obj->lock));
if (WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED))
@@ -998,6 +1001,7 @@ static int msm_gem_new_impl(struct drm_device *dev, uint32_t size, uint32_t flags, struct drm_gem_object **obj) {
struct msm_drm_private *priv = dev->dev_private; struct msm_gem_object *msm_obj;
switch (flags & MSM_BO_CACHE_MASK) {
@@ -1005,6 +1009,10 @@ static int msm_gem_new_impl(struct drm_device *dev, case MSM_BO_CACHED: case MSM_BO_WC: break;
- case MSM_BO_CACHED_COHERENT:
if (priv->has_cached_coherent)break;/* fallthrough */
It confused me that this kind of implicitly fell into the else clause in msm_gem_mmap_obj, but I'm on board. This is a good solution since it only allows I/O coherence with caching.
default: DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n", (flags & MSM_BO_CACHE_MASK)); diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h index a6c1f3eb2623..474497e8743a 100644 --- a/include/uapi/drm/msm_drm.h +++ b/include/uapi/drm/msm_drm.h @@ -94,12 +94,11 @@ struct drm_msm_param { #define MSM_BO_CACHED 0x00010000 #define MSM_BO_WC 0x00020000 #define MSM_BO_UNCACHED 0x00040000 +#define MSM_BO_CACHED_COHERENT 0x080000
#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \ MSM_BO_GPU_READONLY | \
MSM_BO_CACHED | \MSM_BO_WC | \MSM_BO_UNCACHED)
MSM_BO_CACHE_MASK)struct drm_msm_gem_new { __u64 size; /* in */ -- 2.26.1