Hi Rob,
On Mon, Oct 11, 2021 at 07:43:16PM -0500, Rob Herring wrote:
On Mon, Oct 11, 2021 at 11:46:19AM +0200, Markus Schneider-Pargmann wrote:
This controller is present on several mediatek hardware. Currently mt8195 and mt8395 have this controller without a functional difference, so only one compatible field is added.
The controller can have two forms, as a normal display port and as an embedded display port.
Signed-off-by: Markus Schneider-Pargmann msp@baylibre.com
.../display/mediatek/mediatek,dp.yaml | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml new file mode 100644 index 000000000000..f7a35962c23b --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Mediatek Display Port Controller
+maintainers:
- CK Hu ck.hu@mediatek.com
- Jitao shi jitao.shi@mediatek.com
+description: |
- Device tree bindings for the Mediatek (embedded) Display Port controller
- present on some Mediatek SoCs.
+properties:
- compatible:
- enum:
- mediatek,mt8195-edp_tx
- mediatek,mt8195-dp_tx
Are these blocks different?
Good point, the registers of these blocks are described in its own chapter each. Also I do need to distinguish between both in the driver. Would you suggest making this distinction differently or keep it as two compatibles?
- reg:
- maxItems: 1
- interrupts:
- maxItems: 1
- clocks:
- items:
- description: faxi clock
- clock-names:
- items:
- const: faxi
- power-domains:
- maxItems: 1
- ports:
- $ref: /schemas/graph.yaml#/properties/ports
- properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input endpoint of the controller, usually dp_intf
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: Output endpoint of the controller
+required:
- compatible
- reg
- interrupts
- ports
+additionalProperties: false
+examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/power/mt8195-power.h>
- dp_tx: edp_tx@1c500000 {
compatible = "mediatek,mt8195-edp_tx";
reg = <0 0x1c500000 0 0x8000>;
interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
pinctrl-names = "default";
pinctrl-0 = <&edp_pin>;
status = "okay";
Don't show status in examples.
Fixed.
Thank you Rob.
Best, Markus
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_in: endpoint {
remote-endpoint = <&dp_intf0_out>;
};
};
port@1 {
reg = <1>;
edp_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
- };
-- 2.33.0