From: Flora Cui Flora.Cui@amd.com
Change-Id: I6f5dfa4379cb21c41c68757fae0105527a03e54f Signed-off-by: Flora Cui Flora.Cui@amd.com --- tests/amdgpu/basic_tests.c | 175 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 173 insertions(+), 2 deletions(-)
diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index d79859a..649c5a4 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -49,6 +49,7 @@ static void amdgpu_userptr_test(void); static void amdgpu_semaphore_test(void); static void amdgpu_sync_dependency_test(void); static void amdgpu_bo_eviction_test(void); +static void amdgpu_memset_dispatch_test(void); static void amdgpu_direct_gma_test(void);
static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); @@ -71,6 +72,7 @@ CU_TestInfo basic_tests[] = { { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, { "SW semaphore Test", amdgpu_semaphore_test }, { "Sync dependency Test", amdgpu_sync_dependency_test }, + { "Memset dispatch Test", amdgpu_memset_dispatch_test }, { "Direct GMA", amdgpu_direct_gma_test }, CU_TEST_INFO_NULL, }; @@ -119,6 +121,7 @@ CU_TestInfo basic_tests[] = { #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ (((op) & 0xFF) << 8) | \ ((n) & 0x3FFF) << 16) +#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1)
/* Packet 3 types */ #define PACKET3_NOP 0x10 @@ -247,8 +250,8 @@ CU_TestInfo basic_tests[] = { #define PACKET3_SET_SH_REG_START 0x00002c00
#define PACKET3_DISPATCH_DIRECT 0x15 - - +#define PACKET3_EVENT_WRITE 0x46 +#define PACKET3_ACQUIRE_MEM 0x58 /* gfx 8 */ #define mmCOMPUTE_PGM_LO 0x2e0c #define mmCOMPUTE_PGM_RSRC1 0x2e12 @@ -1945,6 +1948,174 @@ static void amdgpu_sync_dependency_test(void) free(ibs_request.dependencies); }
+static const uint32_t bufferclear_cs_shader_gfx9[] = +{ + 0xD1FD0000, 0x04010C08, 0x7E020204, 0x7E040205, + 0x7E060206, 0x7E080207, 0xE01C2000, 0x80000100, + 0xBF810000 +}; +static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = { + {0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 }, + {0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 }, + {0x2e07, 0x00000040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 }, + {0x2e08, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 }, + {0x2e09, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 } +}; +static void amdgpu_memset_dispatch_gfx_test_gfx9() +{ + amdgpu_context_handle context_handle; + amdgpu_bo_handle bo_dst, bo_shader, resources[2]; + volatile unsigned char *ptr_dst; + void *ptr_shader; + uint64_t mc_address_dst, mc_address_shader; + amdgpu_va_handle va_dst, va_shader; + int i, j, r; + uint32_t *ptr; + int bo_dst_size = 16384; + struct amdgpu_cs_request ibs_request; + struct amdgpu_cs_ib_info ib_info; + + ptr = calloc(256, sizeof(*ptr)); + CU_ASSERT_NOT_EQUAL(ptr, NULL); + memset(ptr, 0, 256); + + r = amdgpu_cs_ctx_create(device_handle, &context_handle); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_shader, &ptr_shader, + &mc_address_shader, &va_shader); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096, + AMDGPU_GEM_DOMAIN_VRAM, 0, + &bo_dst, &ptr_dst, + &mc_address_dst, &va_dst); + CU_ASSERT_EQUAL(r, 0); + + memcpy(ptr_shader, bufferclear_cs_shader_gfx9, sizeof(bufferclear_cs_shader_gfx9)); + + i = 0; + ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1); + ptr[i++] = 0x80000000; + ptr[i++] = 0x80000000; + + /* Issue commands to set default compute state. */ + /* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */ + ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3); + ptr[i++] = 0x204; + ptr[i++] = 0; + ptr[i++] = 0; + ptr[i++] = 0; + /* clear mmCOMPUTE_RESOURCE_LIMITS */ + ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1); + ptr[i++] = 0x215; + ptr[i++] = 0; + /* clear mmCOMPUTE_TMPRING_SIZE */ + ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1); + ptr[i++] = 0x218; + ptr[i++] = 0; + + /* Issue commands to set cu mask used in current dispatch */ + /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */ + ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2); + ptr[i++] = 0x216; + ptr[i++] = 0xffffffff; + ptr[i++] = 0xffffffff; + /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */ + ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2); + ptr[i++] = 0x219; + ptr[i++] = 0xffffffff; + ptr[i++] = 0xffffffff; + + /* Writes shader state to HW */ + /* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */ + ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2); + ptr[i++] = 0x20c; + ptr[i++] = (mc_address_shader >> 8); + ptr[i++] = (mc_address_shader >> 40); + /* write sh regs*/ + for (j = 0; j < 5; j++) { + ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1); + /* - Gfx9ShRegBase */ + ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][0] - 0x2c00; + ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][1]; + } + /* Write constant data */ + /* Writes the UAV constant data to the SGPRs. */ + ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4); + ptr[i++] = 0x240; + ptr[i++] = mc_address_dst; + ptr[i++] = (mc_address_dst > 32) | 0x100000; + ptr[i++] = 0x400; + ptr[i++] = 0x74fac; + /* Sets a range of pixel shader constants */ + ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4); + ptr[i++] = 0x244; + ptr[i++] = 0x22222222; + ptr[i++] = 0x22222222; + ptr[i++] = 0x22222222; + ptr[i++] = 0x22222222; + + /* dispatch direct command */ + ptr[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3); + ptr[i++] = 0x10; + ptr[i++] = 1; + ptr[i++] = 1; + ptr[i++] = 1; + + /* Wait for CS to complete and then invalidates L1/L2 cache with SurfaceSync */ + ptr[i++] = PACKET3(PACKET3_EVENT_WRITE, 0); + ptr[i++] = 0x407; + ptr[i++] = PACKET3(PACKET3_ACQUIRE_MEM, 5); + ptr[i++] = 0x80c40000; + ptr[i++] = 0xffffffff; + ptr[i++] = 0xff; + ptr[i++] = 0; + ptr[i++] = 0; + ptr[i++] = 0xa; + + while (i & 7) + ptr[i++] = 0xffff1000; /* type3 nop packet */ + + resources[0] = bo_dst; + resources[1] = bo_shader; + amdgpu_test_exec_cs_helper(context_handle, + AMDGPU_HW_IP_GFX, 0, + i, ptr, + 2, resources, + &ib_info, &ibs_request); + + /* verify if memset test result meets with expected */ + i = 0; + while(i < bo_dst_size) { + CU_ASSERT_EQUAL(ptr_dst[i++], 0x22); + } + + free(ptr); + + r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, 4096); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size); + CU_ASSERT_EQUAL(r, 0); + + r = amdgpu_cs_ctx_free(context_handle); + CU_ASSERT_EQUAL(r, 0); +} + +static void amdgpu_memset_dispatch_test() +{ + struct drm_amdgpu_info_hw_ip info; + int r; + + r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info); + CU_ASSERT_EQUAL(r, 0); + + if (info.hw_ip_version_major == 9) + amdgpu_memset_dispatch_gfx_test_gfx9(); +} + static int amdgpu_direct_gma_bo_alloc_and_map(amdgpu_device_handle dev, amdgpu_device_handle peer, unsigned size, unsigned alignment, amdgpu_bo_handle *bo, amdgpu_bo_handle *bo_peer,