On Wed, Sep 10, 2014 at 12:03 AM, Michel Dänzer michel@daenzer.net wrote:
On 10.09.2014 01:28, Alex Deucher wrote:
On Mon, Sep 8, 2014 at 9:15 PM, Michel Dänzer michel@daenzer.net wrote:
On 09.09.2014 09:47, Michel Dänzer wrote:
On 09.09.2014 02:36, Alex Deucher wrote:
Updated version with comments integrated.
[...]
@@ -314,10 +314,12 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, unsigned lpfn = 0;
/* force to pin into visible video ram */
if (bo->placements[i].flags & TTM_PL_FLAG_VRAM)lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;else
if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) {if (!(bo->flags & RADEON_GEM_NO_CPU_ACCESS))lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;} else { lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */}The else block can be removed as well, but that can be done in another patch.
Actually, I just noticed a problem, the following if statement:
if (max_offset) lpfn = min (lpfn, (unsigned)(max_offset >>PAGE_SHIFT));
This will ignore max_offset if lpfn is 0. So either go with v1 of this hunk, or rebase on top of the patch below.
Rebased on your patch and attached.
My patch didn't handle max_offset == 0 correctly. Attaching a fixed v2 patch and your patch rebased on top of that.
Applied. thanks!
Alex