On Mon, 27 Sept 2021 at 00:42, Dmitry Osipenko digetx@gmail.com wrote:
Add OPP and SoC core voltage scaling support to the display controller driver. This is required for enabling system-wide DVFS on pre-Tegra186 SoCs.
Tested-by: Peter Geis pgwipeout@gmail.com # Ouya T30 Tested-by: Paul Fertser fercerpav@gmail.com # PAZ00 T20 Tested-by: Nicolas Chauvet kwizart@gmail.com # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar mattmerhar@protonmail.com # Ouya T30 Signed-off-by: Dmitry Osipenko digetx@gmail.com
drivers/gpu/drm/tegra/dc.c | 74 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/dc.h | 2 ++ 2 files changed, 76 insertions(+)
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index a29d64f87563..d4047a14e2b6 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -11,9 +11,12 @@ #include <linux/interconnect.h> #include <linux/module.h> #include <linux/of_device.h> +#include <linux/pm_domain.h> +#include <linux/pm_opp.h> #include <linux/pm_runtime.h> #include <linux/reset.h>
+#include <soc/tegra/common.h> #include <soc/tegra/pmc.h>
#include <drm/drm_atomic.h> @@ -1762,6 +1765,47 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc, return 0; }
+static void tegra_dc_update_voltage_state(struct tegra_dc *dc,
struct tegra_dc_state *state)+{
unsigned long rate, pstate;struct dev_pm_opp *opp;int err;if (!dc->has_opp_table)return;/* calculate actual pixel clock rate which depends on internal divider */rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);/* find suitable OPP for the rate */opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);if (opp == ERR_PTR(-ERANGE))opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);if (IS_ERR(opp)) {dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n",rate, opp);return;}pstate = dev_pm_opp_get_required_pstate(opp, 0);dev_pm_opp_put(opp);/** The minimum core voltage depends on the pixel clock rate (which* depends on internal clock divider of the CRTC) and not on the* rate of the display controller clock. This is why we're not using* dev_pm_opp_set_rate() API and instead controlling the power domain* directly.*/err = dev_pm_genpd_set_performance_state(dc->dev, pstate);if (err)dev_err(dc->dev, "failed to set power domain state to %lu: %d\n",pstate, err);
Yeah, the above code looks very similar to the code I pointed to in patch6. Perhaps we need to discuss with Viresh, whether it makes sense to fold in a patch adding an opp helper function after all, to avoid the open coding.
Viresh?
[...]
Kind regards Uffe