-----Original Message----- From: Rob Herring robh@kernel.org Sent: Wednesday, October 7, 2020 6:45 AM To: Chrisanthus, Anitha anitha.chrisanthus@intel.com Cc: dri-devel dri-devel@lists.freedesktop.org; Paauwe, Bob J bob.j.paauwe@intel.com; Dea, Edmund J edmund.j.dea@intel.com; Vetter, Daniel daniel.vetter@intel.com; Sam Ravnborg sam@ravnborg.org Subject: Re: [PATCH v8 1/4] drm/kmb: Keem Bay driver register definition
On Fri, Oct 2, 2020 at 9:17 PM Anitha Chrisanthus anitha.chrisanthus@intel.com wrote:
Register definitions for Keem Bay display driver
v2: removed license text (Sam) v3: Squashed all 59 commits to one v4: review changes from Sam Ravnborg renamed dev_p to kmb v5: corrected spellings v6: corrected checkpatch warnings
Cc: Sam Ravnborg sam@ravnborg.org Signed-off-by: Anitha Chrisanthus anitha.chrisanthus@intel.com Reviewed-by: Bob Paauwe bob.j.paauwe@intel.com
drivers/gpu/drm/kmb/kmb_regs.h | 748
+++++++++++++++++++++++++++++++++++++++++
1 file changed, 748 insertions(+) create mode 100644 drivers/gpu/drm/kmb/kmb_regs.h
diff --git a/drivers/gpu/drm/kmb/kmb_regs.h
b/drivers/gpu/drm/kmb/kmb_regs.h
new file mode 100644 index 0000000..f794ac3 --- /dev/null +++ b/drivers/gpu/drm/kmb/kmb_regs.h @@ -0,0 +1,748 @@ +/* SPDX-License-Identifier: GPL-2.0-only
- Copyright © 2018-2020 Intel Corporation
- */
+#ifndef __KMB_REGS_H__ +#define __KMB_REGS_H__
+#define ENABLE 1 +#define DISABLE 0 +/*from Data Book section 12.5.8.1 page 4322 */ +#define CPR_BASE_ADDR (0x20810000) +#define MIPI_BASE_ADDR (0x20900000) +/*from Data Book section 12.11.6.1 page 4972 */ +#define LCD_BASE_ADDR (0x20930000) +#define MSS_CAM_BASE_ADDR (MIPI_BASE_ADDR +
0x10000)
+#define LCD_MMIO_SIZE (0x3000) +#define MIPI_MMIO_SIZE (0x4000) +#define MSS_CAM_MMIO_SIZE (0x30)
Why are these defines here? They all come from DT.
Will remove, will send v9 soon.
Rob