On Wed, Dec 20, 2017 at 6:22 PM, Kristian Kristensen hoegsberg@google.com wrote:
On Wed, Dec 20, 2017 at 12:41 PM, Miguel Angel Vico mvicomoya@nvidia.com wrote:
On Wed, 20 Dec 2017 11:54:10 -0800 Kristian Høgsberg hoegsberg@gmail.com wrote:
I'd like to see concrete examples of actual display controllers supporting more format layouts than what can be specified with a 64 bit modifier.
The main problem is our tiling and other metadata parameters can't generally fit in a modifier, so we find passing a blob of metadata a more suitable mechanism.
I understand that you may have n knobs with a total of more than a total of 56 bits that configure your tiling/swizzling for color buffers. What I don't buy is that you need all those combinations when passing buffers around between codecs, cameras and display controllers. Even if you're sharing between the same 3D drivers in different processes, I expect just locking down, say, 64 different combinations (you can add more over time) and assigning each a modifier would be sufficient. I doubt you'd extract meaningful performance gains from going all the way to a blob.
There's probably a world of stuff that we don't know about in nouveau, but I have a hard time coming up with more than 64-bits worth of tiling info for dGPU surfaces...
There's 8 bits (sorta, not fully populated, but might as well use them) of "micro" tiling which is done at the PTE level by the memory controller and includes compression settings, and then there's 4 bits of tiling per dimension for macro blocks (which configures different sizes for each dimension for tile sizes) -- that's only 20 bits. MSAA level (which is part of the micro tiling setting usually, but may not necessarily have to be) - another couple of bits, maybe something else weird for another few bits. Anyways, this is *nowhere* close to 64 bits.
What am I missing?
-ilia