On Thursday, August 28, 2014 1:33 PM, Sonika Sonika wrote:
On 8/28/2014 6:25 AM, Jingoo Han wrote:
On Friday, August 08, 2014 7:54 PM, Sonika Jindal wrote:
From: Sonika Jindal sonika.jindal@intel.com
Rename the defines to have levels instead of values for vswing and pre-emph levels as the values may differ in other scenarios like low vswing of eDP1.4 where the values are different.
Done using following cocci patch for each define: @@ @@
# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
- # define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0)
...
Signed-off-by: Sonika Jindal sonika.jindal@intel.com
drivers/gpu/drm/exynos/exynos_dp_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c index 4f3c7eb..02602a8 100644 --- a/drivers/gpu/drm/exynos/exynos_dp_core.c +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c @@ -329,8 +329,8 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) return retval;
for (lane = 0; lane < lane_count; lane++)
buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 |DP_TRAIN_VOLTAGE_SWING_400;
buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |DP_TRAIN_VOLTAGE_SWING_LEVEL_0;NAK!
It makes build error. Please build your patch, before sending the patch. It is a rule when submitting patches.
Please, fix it as follows.
buf[lane] = DP_TRAIN_PRE_EMPHASIS_LEVEL_0|DP_TRAIN_VOLTAGE_SWING_LEVEL_0;I think the first patch which you have taken (which adds new defines) is the one from the previous series for the same change. In the second version, I have named them as DP_TRAIN_PRE_EMPH_LEVEL_* which was done using cocci. Following is from that patch:
Oh, I see. Sorry for annoying you. However, how about tagging V2, V3.. into patches? For instance, '[PATCH V2 3/7] drm/exynos: Renaming DP training vswing pre emph defines' It will be helpful, in order to prevent the same mistakes happening again.
Also, the patch looks good. Acked-by: Jingoo Han jg1.han@samsung.com
Best regards, Jingoo Han
# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) # define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) # define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) # define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3)
Best regards, Jingoo Han
retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, lane_count, buf); -- 1.7.10.4