This reverts commit 5f2fd347eeff7d4ce271920efd47baaa18fe968c.
Re-enable enc2_dp_set_dsc_config. This function caused warnings due to missing register definitions. With the registers added, this now works
Signed-off-by: David Francis David.Francis@amd.com Reviewed-by: Roman Li Roman.Li@amd.com Reviewed-by: Harry Wentland harry.wentland@amd.com Reviewed-by: Nicholas Kazlauskas nicholas.kazlauskas@amd.com --- .../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 8 -------- 1 file changed, 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c index 6d54942ab98b..a4e67286cdad 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c @@ -277,14 +277,6 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc, uint32_t dsc_slice_width) { struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t dsc_value = 0; - - dsc_value = REG_READ(DP_DSC_CNTL); - - /* dsc disable skip */ - if ((dsc_value & 0x3) == 0x0) - return; -
REG_UPDATE_2(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode,