On Mon, Jun 9, 2014 at 3:38 PM, Fabio Estevam festevam@gmail.com wrote:
On Mon, Jun 9, 2014 at 3:15 PM, Fabio Estevam festevam@gmail.com wrote:
I wonder if the problem is that HDMI and LVDS are interfering with each other wrt the required pixel clock, and LVDS is winning. If we have HDMI enabled, many HDMI sinks will only work if we set one of their supported modes (with the dot clock within 1% - though some sinks are more lenient).
Yes, it seems this is the case.
I tested not using pll5 as the parent of LVDS:
--- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -439,12 +439,6 @@ static void __init imx6q_clocks_init(struct device_node *cc clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); clk_register_clkdev(clk[enet_ref], "enet_ref", NULL);
if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||cpu_is_imx6dl()) {clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);}clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);Then the HDMI detection works fine and I get images on both HDMI and LVDS.
I understand that many LVDS panels need a frequency range that can only be obtained via PLL5 though.
Also tested keeping LVDS parent as PLL5 and reverted this commit:
commit 17b9b3b9e88ac6564689283a08034faf2c048fdb Author: Sascha Hauer s.hauer@pengutronix.de Date: Mon Apr 14 16:20:39 2014 +0200
ARM: imx6q: clk: Parent DI clocks to video PLL via di_pre_sel
Route the video PLL to the display interface clocks via the di_pre_sel and di_sel muxes by default.
Signed-off-by: Sascha Hauer s.hauer@pengutronix.de Signed-off-by: Philipp Zabel p.zabel@pengutronix.de Tested-by: Russell King rmk+kernel@arm.linux.org.uk Signed-off-by: Shawn Guo shawn.guo@freescale.com
,then HDMI and LVDS work at the same time.