Re: [Intel-gfx] [PATCH 3/7] drm/i915: Treat PCH eDP like DP in most places

On Wed, 2 Nov 2011 09:20:19 -0700, Jesse Barnes jbarnes@virtuousgeek.org wrote:

But I was curious about this hunk:

@@ -766,10 +766,10 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, continue;

intel_dp = enc_to_intel_dp(encoder);

• if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
  

• if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || is_pch_edp(intel_dp)) {
  lane_count = intel_dp->lane_count;
  break;
  

• } else if (is_edp(intel_dp)) {
  

• } else if (is_cpu_edp(intel_dp)) {
  lane_count = dev_priv->edp.lanes;
  break;
  

  }

I guess this means we can't trust the BIOS settings for PCH eDP?

I'm pretty sure this isn't the right place to look at this value in any case; we're setting the m/n ratios after already deciding how many lanes to use. Getting this wrong means sending the wrong timing to the monitor, not setting a different mode.

In any case, my AIO box sets the BIOS value to 1, when it needs 2 lanes for the mode it uses.