On 06/12/2021 14:49, Daniel Stone wrote:
Hi Matthew,
On Mon, 6 Dec 2021 at 13:32, Matthew Auld matthew.auld@intel.com wrote:
Enable accelerated moves and clearing on DG2. On such HW we have minimum page size restrictions when accessing LMEM from the GTT, where we now have to use 64K GTT pages or larger. With the ppGTT the page-table also has a slightly different layout from past generations when using the 64K GTT mode(which is still enabled on via some PDE bit), where it is now compacted down to 32 qword entries. Note that on discrete the paging structures must also be placed in LMEM, and we need to able to modify them via the GTT itself(see patch 7), which is one of the complications here.
The series needs to be applied on top of the DG2 enabling branch: https://cgit.freedesktop.org/~ramaling/linux/log/?h=dg2_enabling_ww49.3
What are the changes to the v1/v2?
Yeah, I should have added that somewhere. Sorry.
v2: Add missing cover letter v3: - Add some r-b tags - Drop the GTT_MAPPABLE approach. We can instead simply pass along the required size/alignment using alloc_pt().
Cheers, Daniel