于 2020年2月22日 GMT+08:00 上午1:13:28, Torsten Duwe duwe@lst.de 写到:
On Sat, Feb 22, 2020 at 12:51:27AM +0800, Icenowy Zheng wrote:
Current code tries to store the link rate (in bps, which is a big number) in a u8, which surely overflow. Then it's converted back to bandwidth code (which is thus 0) and written to the chip.
The code sometimes works because the chip will automatically fallback
to
the lowest possible DP link rate (1.62Gbps) when get the invalid
value.
However, on the eDP panel of Olimex TERES-I, which wants 2.7Gbps
link,
it failed.
As we had already read the link bandwidth as bandwidth code in
earlier
code (to check whether it is supported), use it when setting
bandwidth,
instead of converting it to link rate and then converting back.
Fixes: e1cff82c1097 ("drm/bridge: fix anx6345 compilation for v5.5") Signed-off-by: Icenowy Zheng icenowy@aosc.io
drivers/gpu/drm/bridge/analogix/analogix-anx6345.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c
index 56f55c53abfd..2dfa2fd2a23b 100644 --- a/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c +++ b/drivers/gpu/drm/bridge/analogix/analogix-anx6345.c @@ -210,8 +210,7 @@ static int anx6345_dp_link_training(struct
anx6345 *anx6345)
if (err) return err;
- dpcd[0] = drm_dp_max_link_rate(anx6345->dpcd);
- dpcd[0] = drm_dp_link_rate_to_bw_code(dpcd[0]);
- dpcd[0] = dp_bw;
Why do you make this assignment and not use dp_bw directly in the call?
Because the dpcd array is then written as a continous array back to DPCD.
err = regmap_write(anx6345->map[I2C_IDX_DPTX], SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]);
^^^^^^if (err)
2.24.1
BTW, my version is only a bit more verbose:
https://patchwork.freedesktop.org/patch/354344/
Torsten