On Thu, Oct 27, 2011 at 12:12:09PM -0400, Alex Deucher wrote:
On Wed, Oct 26, 2011 at 11:41 AM, j.glisse@gmail.com wrote:
From: Jerome Glisse jglisse@redhat.com
Cayman seems to be particularly sensitive to read cache returning old data after bind/unbind to GTT. Flush read cache for GTT range with each fences for all new hw. Should fix several rendering glitches. Like
V2 flush whole address space V3 also flush shader read cache
https://bugs.freedesktop.org/show_bug.cgi?id=40221 https://bugs.freedesktop.org/show_bug.cgi?id=38022 https://bugzilla.redhat.com/show_bug.cgi?id=738790
Signed-off-by: Jerome Glisse jglisse@redhat.com
drivers/gpu/drm/radeon/evergreen_blit_kms.c | 4 ++-- drivers/gpu/drm/radeon/r600.c | 16 ++++++++++++++++ drivers/gpu/drm/radeon/r600_blit_kms.c | 4 ++-- 3 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c index dcf11bb..e9aeeed 100644 --- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c +++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c @@ -613,9 +613,9 @@ int evergreen_blit_init(struct radeon_device *rdev) rdev->r600_blit.primitives.set_default_state = set_default_state;
rdev->r600_blit.ring_size_common = 55; /* shaders + def state */
- rdev->r600_blit.ring_size_common += 10; /* fence emit for VB IB */
- rdev->r600_blit.ring_size_common += 16; /* fence emit for VB IB */
rdev->r600_blit.ring_size_common += 5; /* done copy */
- rdev->r600_blit.ring_size_common += 10; /* fence emit for done copy */
- rdev->r600_blit.ring_size_common += 16; /* fence emit for done copy */
rdev->r600_blit.ring_size_per_loop = 74;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 12470b0..1f007ad 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -2331,6 +2331,14 @@ void r600_fence_ring_emit(struct radeon_device *rdev, if (rdev->wb.use_event) { u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET + (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
We need to specify the vmid on cayman, so we should probably add the following here:
if (rdev->family >= CHIP_CAYMAN) { /* CP_COHER_CNTL2 has to be set manually whensubmitting a surface_sync * to the RB directly. For IBs, the CP programs this as part of the * surface_sync packet. */ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); radeon_ring_write(rdev, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2); radeon_ring_write(rdev, 0); /* CP_COHER_CNTL2 */ }
I think default cayman blit state already does specify vmid so we should be fine.
Cheers, Jerome