On Mon, 10 Jan 2022 at 15:56, Rajeev Nandan quic_rajeevny@quicinc.com wrote:
Add support for MSM DSI PHY tuning configuration. Current design is to support drive strength and drive level/amplitude tuning for 10nm PHY version, but this can be extended to other PHY versions.
Signed-off-by: Rajeev Nandan quic_rajeevny@quicinc.com
Changes in v2:
- New.
- Split into generic code and 10nm-specific part (Dmitry Baryshkov)
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 3 +++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 16 ++++++++++++++++ 2 files changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 8c65ef6..ee3739d 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -739,6 +739,9 @@ static int dsi_phy_driver_probe(struct platform_device *pdev) } }
if (phy->cfg->ops.tuning_cfg_init)phy->cfg->ops.tuning_cfg_init(phy);
Please rename to parse_dt_properties() or something like that.
ret = dsi_phy_regulator_init(phy); if (ret) goto fail;diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index b91303a..b559a2b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -25,6 +25,7 @@ struct msm_dsi_phy_ops { void (*save_pll_state)(struct msm_dsi_phy *phy); int (*restore_pll_state)(struct msm_dsi_phy *phy); bool (*set_continuous_clock)(struct msm_dsi_phy *phy, bool enable);
void (*tuning_cfg_init)(struct msm_dsi_phy *phy);};
struct msm_dsi_phy_cfg { @@ -81,6 +82,20 @@ struct msm_dsi_dphy_timing { #define DSI_PIXEL_PLL_CLK 1 #define NUM_PROVIDED_CLKS 2
+#define DSI_LANE_MAX 5
+/**
- struct msm_dsi_phy_tuning_cfg - Holds PHY tuning config parameters.
- @rescode_offset_top: Offset for pull-up legs rescode.
- @rescode_offset_bot: Offset for pull-down legs rescode.
- @vreg_ctrl: vreg ctrl to drive LDO level
- */
+struct msm_dsi_phy_tuning_cfg {
u8 rescode_offset_top[DSI_LANE_MAX];u8 rescode_offset_bot[DSI_LANE_MAX];u8 vreg_ctrl;+};
How generic is this? In other words, you are adding a struct with the generic name to the generic structure. I'd expect that it would be common to several PHY generations.
struct msm_dsi_phy { struct platform_device *pdev; void __iomem *base; @@ -98,6 +113,7 @@ struct msm_dsi_phy {
struct msm_dsi_dphy_timing timing; const struct msm_dsi_phy_cfg *cfg;
struct msm_dsi_phy_tuning_cfg tuning_cfg; enum msm_dsi_phy_usecase usecase; bool regulator_ldo_mode;-- 2.7.4