Split things out a little and add the IVB reg definitions.
Signed-off-by: Jesse Barnes jbarnes@virtuousgeek.org --- drivers/gpu/drm/i915/i915_reg.h | 59 ++++++++++++ drivers/gpu/drm/i915/intel_overlay2.c | 168 ++++++++++++++++++++++++++++++-- 2 files changed, 216 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7b128d4..71496b8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2718,6 +2718,65 @@ #define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE) #define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
+#define _SPRA_CTL 0x70280 +#define SPRITE_ENABLE (1<<31) +#define SPRITE_GAMMA_ENABLE (1<<30) +#define SPRITE_PIXFORMAT_MASK (7<<25) +#define SPRITE_FORMAT_YUV422 (0<<25) +#define SPRITE_FORMAT_RGBX101010 (1<<25) +#define SPRITE_FORMAT_RGBX888 (2<<25) +#define SPRITE_FORMAT_RGBX161616 (3<<25) +#define SPRITE_FORMAT_YUV444 (4<<25) +#define SPRITE_FORMAT_XBGR101010 (5<<25) +#define SPRITE_CSC_ENABLE (1<<24) +#define SPRITE_SOURCE_KEY (1<<22) +#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */ +#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19) +#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */ +#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16) +#define SPRITE_YUV_ORDER_YUYV (0<<16) +#define SPRITE_YUV_ORDER_UYVY (1<<16) +#define SPRITE_YUV_ORDER_YVYU (2<<16) +#define SPRITE_YUV_ORDER_VYUY (3<<16) +#define SPRITE_TRICKLE_FEED_DISABLE (1<<14) +#define SPRITE_INT_GAMMA_ENABLE (1<<13) +#define SPRITE_TILED (1<<10) +#define SPRITE_DEST_KEY (1<<2) +#define _SPRA_STRIDE 0x70288 +#define _SPRA_POS 0x7028c +#define _SPRA_SIZE 0x70290 +#define _SPRA_KEYVAL 0x70294 +#define _SPRA_KEYMSK 0x70298 +#define _SPRA_SURF 0x7029c +#define _SPRA_KEYMAX 0x702a0 +#define _SPRA_TILEOFF 0x702a4 +#define _SPRA_SCALE 0x70304 +#define _SPRA_GAMC 0x70400 + +#define _SPRB_CTL 0x70280 +#define _SPRB_STRIDE 0x70288 +#define _SPRB_POS 0x7028c +#define _SPRB_SIZE 0x70290 +#define _SPRB_KEYVAL 0x70294 +#define _SPRB_KEYMSK 0x70298 +#define _SPRB_SURF 0x7029c +#define _SPRB_KEYMAX 0x702a0 +#define _SPRB_TILEOFF 0x702a4 +#define _SPRB_SCALE 0x70304 +#define _SPRB_GAMC 0x70400 + +#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL) +#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) +#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS) +#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) +#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) +#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) +#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF) +#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) +#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) +#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) +#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + /* VBIOS regs */ #define VGACNTRL 0x71400 # define VGA_DISP_DISABLE (1 << 31) diff --git a/drivers/gpu/drm/i915/intel_overlay2.c b/drivers/gpu/drm/i915/intel_overlay2.c index 861e09e..61b1a2f 100644 --- a/drivers/gpu/drm/i915/intel_overlay2.c +++ b/drivers/gpu/drm/i915/intel_overlay2.c @@ -36,7 +36,116 @@ #include "i915_drv.h"
static int -intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, +ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, + struct drm_framebuffer *fb, int crtc_x, int crtc_y, + unsigned int crtc_w, unsigned int crtc_h, + uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h) +{ + struct drm_device *dev = plane->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_plane *intel_plane = to_intel_plane(plane); + struct intel_framebuffer *intel_fb; + struct drm_i915_gem_object *obj, *old_obj; + int pipe = intel_plane->pipe; + unsigned long start, offset; + u32 sprctl; + u32 reg = SPRCTL(pipe); + int ret = 0; + int x = src_x >> 16, y = src_y >> 16; + + assert_pipe_enabled(dev_priv, pipe); + + intel_fb = to_intel_framebuffer(fb); + obj = intel_fb->obj; + + old_obj = intel_plane->obj; + + mutex_lock(&dev->struct_mutex); + + sprctl = I915_READ(reg); + + /* Mask out pixel format bits in case we change it */ + sprctl &= ~(SPRITE_DEST_KEY | SPRITE_SOURCE_KEY); + sprctl &= ~SPRITE_PIXFORMAT_MASK; + sprctl &= ~SPRITE_RGB_ORDER_RGBX; + sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK; + + switch (fb->pixel_format) { + case V4L2_PIX_FMT_BGR32: + sprctl |= SPRITE_FORMAT_RGBX888; + break; + case V4L2_PIX_FMT_RGB32: + sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; + break; + case V4L2_PIX_FMT_YUYV: + sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; + break; + case V4L2_PIX_FMT_YVYU: + sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; + break; + case V4L2_PIX_FMT_UYVY: + sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; + break; + case V4L2_PIX_FMT_VYUY: + sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; + break; + default: + ret = -EINVAL; + DRM_ERROR("bad pixel format\n"); + goto out_unlock; + } + + if (obj->tiling_mode != I915_TILING_X) { + DRM_ERROR("plane surfaces must be X tiled\n"); + ret = -EINVAL; + goto out_unlock; + } + + ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); + if (ret) + goto out_unlock; + + intel_plane->obj = obj; + + sprctl |= SPRITE_TILED; + + /* must disable */ + sprctl |= SPRITE_TRICKLE_FEED_DISABLE; + sprctl |= SPRITE_ENABLE; + + start = obj->gtt_offset; + offset = y * fb->pitch + x * (fb->bits_per_pixel / 8); + + DRM_ERROR("enabling sprite, pos %d,%d, size %dx%d\n", + crtc_x, crtc_y, fb->width, fb->height); + + I915_WRITE(SPRSTRIDE(pipe), fb->pitch); + I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x); + I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x); + I915_WRITE(SPRSIZE(pipe), (fb->height << 16) | fb->width); + I915_WRITE(SPRSCALE(pipe), 0); + I915_WRITE(reg, sprctl); + I915_WRITE(SPRSURF(pipe), start); + POSTING_READ(SPRSURF(pipe)); + + /* Adjust watermarks as needed */ + I915_WRITE(WM1S_LP_ILK, 0x100); + + /* Unpin old obj after new one is active to avoid ugliness */ + if (old_obj) { + intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); + i915_gem_object_unpin(old_obj); + } + +out_unlock: + mutex_unlock(&dev->struct_mutex); + + return ret; +} + +static int +snb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, struct drm_framebuffer *fb, int crtc_x, int crtc_y, unsigned int crtc_w, unsigned int crtc_h, uint32_t src_x, uint32_t src_y, @@ -66,6 +175,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, dvscntr = I915_READ(reg);
/* Mask out pixel format bits in case we change it */ + dvscntr &= ~(DVS_DEST_KEY | DVS_SOURCE_KEY); dvscntr &= ~DVS_PIXFORMAT_MASK; dvscntr &= ~DVS_RGB_ORDER_RGBX; dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; @@ -91,12 +201,12 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, break; default: ret = -EINVAL; - DRM_DEBUG_KMS("bad pixel format\n"); + DRM_ERROR("bad pixel format\n"); goto out_unlock; }
if (obj->tiling_mode != I915_TILING_X) { - DRM_DEBUG_KMS("plane surfaces must be X tiled\n"); + DRM_ERROR("plane surfaces must be X tiled\n"); ret = -EINVAL; goto out_unlock; } @@ -111,7 +221,6 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
/* must disable */ dvscntr |= DVS_TRICKLE_FEED_DISABLE; - dvscntr |= DVS_DEST_KEY; dvscntr |= DVS_ENABLE;
start = obj->gtt_offset; @@ -139,7 +248,39 @@ out_unlock: }
static int -intel_disable_plane(struct drm_plane *plane) +ivb_disable_plane(struct drm_plane *plane) +{ + struct drm_device *dev = plane->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_plane *intel_plane = to_intel_plane(plane); + int pipe = intel_plane->pipe; + int ret = 0; + + mutex_lock(&dev->struct_mutex); + + if (!intel_plane->obj) + goto out_unlock; +#if 0 + ret = i915_gem_object_finish_gpu(intel_plane->obj); + if (ret) + goto out_unlock; + + i915_gem_object_unpin(intel_plane->obj); +#endif +out_unlock: + intel_plane->obj = NULL; + + I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); + I915_WRITE(SPRSURF(pipe), 0); + POSTING_READ(SPRSURF(pipe)); + + mutex_unlock(&dev->struct_mutex); + + return ret; +} + +static int +snb_disable_plane(struct drm_plane *plane) { struct drm_device *dev = plane->dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -170,10 +311,7 @@ out_unlock: return ret; }
-static const struct drm_plane_funcs intel_plane_funcs = { - .update_plane = intel_update_plane, - .disable_plane = intel_disable_plane, -}; +static struct drm_plane_funcs intel_plane_funcs;
static uint32_t snb_plane_formats[] = { V4L2_PIX_FMT_BGR32, @@ -190,8 +328,8 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe) struct intel_plane *intel_plane; unsigned long possible_crtcs;
- if (!IS_GEN6(dev)) { - DRM_ERROR("new plane code only for SNB\n"); + if (!(IS_GEN6(dev) || IS_GEN7(dev))) { + DRM_ERROR("new plane code only for SNB+\n"); return -ENODEV; }
@@ -199,6 +337,14 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe) if (!intel_plane) return -ENOMEM;
+ if (IS_GEN6(dev)) { + intel_plane_funcs.update_plane = snb_update_plane; + intel_plane_funcs.disable_plane = snb_disable_plane; + } else if (IS_GEN7(dev)) { + intel_plane_funcs.update_plane = ivb_update_plane; + intel_plane_funcs.disable_plane = ivb_disable_plane; + } + intel_plane->pipe = pipe; possible_crtcs = (1 << pipe); drm_plane_init(dev, &intel_plane->base, possible_crtcs,