Quoting Sandeep Maheswaram (2020-04-01 23:38:52)
Convert QMP PHY bindings to DT schema format using json-schema.
Signed-off-by: Sandeep Maheswaram sanm@codeaurora.org
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 332 +++++++++++++++++++++ .../devicetree/bindings/phy/qcom-qmp-phy.txt | 242 --------------- 2 files changed, 332 insertions(+), 242 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml new file mode 100644 index 0000000..18a8985 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -0,0 +1,332 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+title: Qualcomm QMP PHY controller
+maintainers:
- Manu Gautam mgautam@codeaurora.org
+description:
- QMP phy controller supports physical layer functionality for a number of
- controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+properties:
- compatible:
- enum:
- qcom,ipq8074-qmp-pcie-phy- qcom,msm8996-qmp-pcie-phy- qcom,msm8996-qmp-ufs-phy- qcom,msm8996-qmp-usb3-phy- qcom,msm8998-qmp-pcie-phy- qcom,msm8998-qmp-ufs-phy- qcom,msm8998-qmp-usb3-phy- qcom,sdm845-qhp-pcie-phy- qcom,sdm845-qmp-pcie-phy- qcom,sdm845-qmp-ufs-phy- qcom,sdm845-qmp-usb3-phy- qcom,sdm845-qmp-usb3-uni-phy- qcom,sm8150-qmp-ufs-phy- reg:
- minItems: 1
- items:
- description: Address and length of PHY's common serdes block.- description: Address and length of the DP_COM control block.
This DP_COM block is only for one compatible. Is it possible to split that compatible out of this binding so we can enforce the reg property being either one or two items?
In addition, I don't quite understand how this binding is supposed to work with the DP phy that sits inside qcom,sdm845-qmp-usb3-phy and then gets muxed out on the USB pins on sdm845 and sc7180 SoCs. Can you fill me in on how we plan to share the pins between the two phys so that all the combinations of DP and USB over the type-c pins will work here? My understanding is that the pins that are controlled by this hardware block are basically a full USB type-c connector pinout[1] (except that D+/D- isn't there and the VBUS and CC lines go to the PMIC). Either way, we get the TX1/2 and RX1/2 pins to use, so we can do 4x lanes of DP or 2x lanes DP and 2x lanes of USB. There's also a type-c orientation flipper bit that can flip the DP and USB phy lanes to the correct TX/RX pins on the SoC. And then the DP phy has a lane remapper to change the logical DP lane to the physical DP lane. It's a complex piece of hardware that isn't fully represented by this binding.
[1] https://en.wikipedia.org/wiki/USB-C#/media/File:USB_Type-C_Receptacle_Pinout...