From: Alex Deucher alexander.deucher@amd.com
This adds dpm support for trinity asics. This includes: - clockgating - powergating - dynamic engine clock scaling - dynamic voltage scaling
set radeon.dpm=1 to enable it.
Signed-off-by: Alex Deucher alexander.deucher@amd.com --- drivers/gpu/drm/radeon/Makefile | 3 +- drivers/gpu/drm/radeon/evergreen.c | 13 +- drivers/gpu/drm/radeon/evergreend.h | 10 + drivers/gpu/drm/radeon/ppsmc.h | 10 +- drivers/gpu/drm/radeon/radeon_asic.c | 12 + drivers/gpu/drm/radeon/radeon_asic.h | 12 + drivers/gpu/drm/radeon/radeon_pm.c | 1 + drivers/gpu/drm/radeon/sumo_dpm.c | 90 +- drivers/gpu/drm/radeon/sumo_dpm.h | 21 +- drivers/gpu/drm/radeon/sumo_smc.c | 2 - drivers/gpu/drm/radeon/trinity_dpm.c | 1613 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/radeon/trinity_dpm.h | 110 +++ drivers/gpu/drm/radeon/trinity_smc.c | 110 +++ drivers/gpu/drm/radeon/trinityd.h | 223 +++++ 14 files changed, 2179 insertions(+), 51 deletions(-) create mode 100644 drivers/gpu/drm/radeon/trinity_dpm.c create mode 100644 drivers/gpu/drm/radeon/trinity_dpm.h create mode 100644 drivers/gpu/drm/radeon/trinity_smc.c create mode 100644 drivers/gpu/drm/radeon/trinityd.h
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 7c77e1d..2239ec2 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -78,7 +78,8 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ si_blit_shaders.o radeon_prime.o radeon_uvd.o cik.o cik_blit_shaders.o \ r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \ - rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o + rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \ + trinity_smc.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index c91b1e5..6449953 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -4187,8 +4187,12 @@ int evergreen_irq_set(struct radeon_device *rdev) hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN; hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; - thermal_int = RREG32(CG_THERMAL_INT) & - ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); + if (rdev->family == CHIP_ARUBA) + thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) & + ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); + else + thermal_int = RREG32(CG_THERMAL_INT) & + ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; @@ -4360,7 +4364,10 @@ int evergreen_irq_set(struct radeon_device *rdev) WREG32(DC_HPD4_INT_CONTROL, hpd4); WREG32(DC_HPD5_INT_CONTROL, hpd5); WREG32(DC_HPD6_INT_CONTROL, hpd6); - WREG32(CG_THERMAL_INT, thermal_int); + if (rdev->family == CHIP_ARUBA) + WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int); + else + WREG32(CG_THERMAL_INT, thermal_int);
WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 93b91a3..35e6153 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -823,6 +823,16 @@ #define THERM_INT_MASK_HIGH (1 << 24) #define THERM_INT_MASK_LOW (1 << 25)
+#define TN_CG_THERMAL_INT_CTRL 0x738 +#define TN_DIG_THERM_INTH(x) ((x) << 0) +#define TN_DIG_THERM_INTH_MASK 0x000000FF +#define TN_DIG_THERM_INTH_SHIFT 0 +#define TN_DIG_THERM_INTL(x) ((x) << 8) +#define TN_DIG_THERM_INTL_MASK 0x0000FF00 +#define TN_DIG_THERM_INTL_SHIFT 8 +#define TN_THERM_INT_MASK_HIGH (1 << 24) +#define TN_THERM_INT_MASK_LOW (1 << 25) + #define CG_MULT_THERMAL_STATUS 0x740 #define ASIC_T(x) ((x) << 16) #define ASIC_T_MASK 0x07FF0000 diff --git a/drivers/gpu/drm/radeon/ppsmc.h b/drivers/gpu/drm/radeon/ppsmc.h index 638de17..8ef479a 100644 --- a/drivers/gpu/drm/radeon/ppsmc.h +++ b/drivers/gpu/drm/radeon/ppsmc.h @@ -69,7 +69,15 @@ typedef uint8_t PPSMC_Result; #define PPSMC_MSG_ExitULV ((uint8_t)0x65) #define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84)
-typedef uint8_t PPSMC_Msg; +/* TN */ +#define PPSMC_MSG_DPM_Config ((uint32_t) 0x102) +#define PPSMC_MSG_DPM_ForceState ((uint32_t) 0x104) +#define PPSMC_MSG_PG_SIMD_Config ((uint32_t) 0x108) +#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint32_t) 0x11d) +#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint32_t) 0x11e) + + +typedef uint16_t PPSMC_Msg;
#pragma pack(pop)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 8b541b4..5dcbb28 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -1944,6 +1944,18 @@ static struct radeon_asic trinity_asic = { .set_uvd_clocks = &sumo_set_uvd_clocks, .get_temperature = &tn_get_temp, }, + .dpm = { + .init = &trinity_dpm_init, + .setup_asic = &trinity_dpm_setup_asic, + .enable = &trinity_dpm_enable, + .disable = &trinity_dpm_disable, + .set_power_state = &trinity_dpm_set_power_state, + .display_configuration_changed = &trinity_dpm_display_configuration_changed, + .fini = &trinity_dpm_fini, + .get_sclk = &trinity_dpm_get_sclk, + .get_mclk = &trinity_dpm_get_mclk, + .print_power_state = &trinity_dpm_print_power_state, + }, .pflip = { .pre_page_flip = &evergreen_pre_page_flip, .page_flip = &evergreen_page_flip, diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index f6c0984..4d3f93d 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h @@ -581,6 +581,18 @@ bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
+int trinity_dpm_init(struct radeon_device *rdev); +int trinity_dpm_enable(struct radeon_device *rdev); +void trinity_dpm_disable(struct radeon_device *rdev); +int trinity_dpm_set_power_state(struct radeon_device *rdev); +void trinity_dpm_setup_asic(struct radeon_device *rdev); +void trinity_dpm_display_configuration_changed(struct radeon_device *rdev); +void trinity_dpm_fini(struct radeon_device *rdev); +u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low); +u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low); +void trinity_dpm_print_power_state(struct radeon_device *rdev, + struct radeon_ps *ps); + /* DCE6 - SI */ void dce6_bandwidth_update(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index b924bcc1..e6fce0b 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -1055,6 +1055,7 @@ int radeon_pm_init(struct radeon_device *rdev) case CHIP_BARTS: case CHIP_TURKS: case CHIP_CAICOS: + case CHIP_ARUBA: if (radeon_dpm == 1) rdev->pm.pm_method = PM_METHOD_DPM; else diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c b/drivers/gpu/drm/radeon/sumo_dpm.c index 4f49450..67c85c7 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.c +++ b/drivers/gpu/drm/radeon/sumo_dpm.c @@ -27,7 +27,6 @@ #include "r600_dpm.h" #include "cypress_dpm.h" #include "sumo_dpm.h" -#include "atom.h"
#define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5 #define SUMO_MINIMUM_ENGINE_CLOCK 800 @@ -144,7 +143,7 @@ static void sumo_program_grsd(struct radeon_device *rdev) WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u)); }
-static void sumo_gfx_clockgating_initialize(struct radeon_device *rdev) +void sumo_gfx_clockgating_initialize(struct radeon_device *rdev) { sumo_program_git(rdev); sumo_program_grsd(rdev); @@ -452,17 +451,17 @@ static void sumo_program_tp(struct radeon_device *rdev) WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); }
-static void sumo_program_vc(struct radeon_device *rdev) +void sumo_program_vc(struct radeon_device *rdev, u32 vrc) { - WREG32(CG_FTV, SUMO_VRC_DFLT); + WREG32(CG_FTV, vrc); }
-static void sumo_clear_vc(struct radeon_device *rdev) +void sumo_clear_vc(struct radeon_device *rdev) { WREG32(CG_FTV, 0); }
-static void sumo_program_sstp(struct radeon_device *rdev) +void sumo_program_sstp(struct radeon_device *rdev) { u32 p, u; u32 xclk = sumo_get_xclk(rdev); @@ -812,7 +811,7 @@ static void sumo_program_bootup_state(struct radeon_device *rdev) sumo_power_level_enable(rdev, i, false); }
-static void sumo_take_smu_control(struct radeon_device *rdev, bool enable) +void sumo_take_smu_control(struct radeon_device *rdev, bool enable) { u32 v = RREG32(DOUT_SCRATCH3);
@@ -933,14 +932,14 @@ static void sumo_force_nbp_state(struct radeon_device *rdev) } }
-static u32 sumo_get_sleep_divider_from_id(u32 id) +u32 sumo_get_sleep_divider_from_id(u32 id) { return 1 << id; }
-static u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, - u32 sclk, - u32 min_sclk_in_sr) +u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, + u32 sclk, + u32 min_sclk_in_sr) { struct sumo_power_info *pi = sumo_get_pi(rdev); u32 i; @@ -1136,7 +1135,7 @@ int sumo_dpm_enable(struct radeon_device *rdev) sumo_program_power_level_enter_state(rdev); sumo_enable_voltage_scaling(rdev, true); sumo_program_sstp(rdev); - sumo_program_vc(rdev); + sumo_program_vc(rdev, SUMO_VRC_DFLT); sumo_override_cnb_thermal_events(rdev); sumo_start_dpm(rdev); sumo_wait_for_level_0(rdev); @@ -1393,23 +1392,25 @@ static int sumo_parse_power_table(struct radeon_device *rdev) return 0; }
-static u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, u32 vid_2bit) +u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, + struct sumo_vid_mapping_table *vid_mapping_table, + u32 vid_2bit) { - struct sumo_power_info *pi = sumo_get_pi(rdev); u32 i;
- for (i = 0; i < pi->sys_info.vid_mapping_table.num_entries; i++) { - if (pi->sys_info.vid_mapping_table.entries[i].vid_2bit == vid_2bit) - return pi->sys_info.vid_mapping_table.entries[i].vid_7bit; + for (i = 0; i < vid_mapping_table->num_entries; i++) { + if (vid_mapping_table->entries[i].vid_2bit == vid_2bit) + return vid_mapping_table->entries[i].vid_7bit; }
- return pi->sys_info.vid_mapping_table.entries[pi->sys_info.vid_mapping_table.num_entries - 1].vid_7bit; + return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit; }
static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev, u32 vid_2bit) { - u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, vid_2bit); + struct sumo_power_info *pi = sumo_get_pi(rdev); + u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
if (vid_7bit > 0x7C) return 0; @@ -1418,71 +1419,71 @@ static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev, }
static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev, + struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table, ATOM_CLK_VOLT_CAPABILITY *table) { - struct sumo_power_info *pi = sumo_get_pi(rdev); u32 i;
for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { if (table[i].ulMaximumSupportedCLK == 0) break;
- pi->sys_info.disp_clk_voltage_mapping_table.display_clock_frequency[i] = + disp_clk_voltage_mapping_table->display_clock_frequency[i] = table[i].ulMaximumSupportedCLK; }
- pi->sys_info.disp_clk_voltage_mapping_table.num_max_voltage_levels = i; + disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
- if (pi->sys_info.disp_clk_voltage_mapping_table.num_max_voltage_levels == 0) { - pi->sys_info.disp_clk_voltage_mapping_table.display_clock_frequency[0] = 80000; - pi->sys_info.disp_clk_voltage_mapping_table.num_max_voltage_levels = 1; + if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) { + disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000; + disp_clk_voltage_mapping_table->num_max_voltage_levels = 1; } }
-static void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, - ATOM_AVAILABLE_SCLK_LIST *table) +void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, + struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, + ATOM_AVAILABLE_SCLK_LIST *table) { - struct sumo_power_info *pi = sumo_get_pi(rdev); u32 i; u32 n = 0; u32 prev_sclk = 0;
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { if (table[i].ulSupportedSCLK > prev_sclk) { - pi->sys_info.sclk_voltage_mapping_table.entries[n].sclk_frequency = + sclk_voltage_mapping_table->entries[n].sclk_frequency = table[i].ulSupportedSCLK; - pi->sys_info.sclk_voltage_mapping_table.entries[n].vid_2bit = + sclk_voltage_mapping_table->entries[n].vid_2bit = table[i].usVoltageIndex; prev_sclk = table[i].ulSupportedSCLK; n++; } }
- pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries = n; + sclk_voltage_mapping_table->num_max_dpm_entries = n; }
-static void sumo_construct_vid_mapping_table(struct radeon_device *rdev, - ATOM_AVAILABLE_SCLK_LIST *table) +void sumo_construct_vid_mapping_table(struct radeon_device *rdev, + struct sumo_vid_mapping_table *vid_mapping_table, + ATOM_AVAILABLE_SCLK_LIST *table) { - struct sumo_power_info *pi = sumo_get_pi(rdev); u32 i, j;
for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) { if (table[i].ulSupportedSCLK != 0) { - pi->sys_info.vid_mapping_table.entries[table[i].usVoltageIndex].vid_7bit = + vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit = table[i].usVoltageID; - pi->sys_info.vid_mapping_table.entries[table[i].usVoltageIndex].vid_2bit = + vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit = table[i].usVoltageIndex; } }
for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) { - if (pi->sys_info.vid_mapping_table.entries[i].vid_7bit == 0) { + if (vid_mapping_table->entries[i].vid_7bit == 0) { for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) { - if (pi->sys_info.vid_mapping_table.entries[j].vid_7bit != 0) { - pi->sys_info.vid_mapping_table.entries[i] = - pi->sys_info.vid_mapping_table.entries[j]; - pi->sys_info.vid_mapping_table.entries[j].vid_7bit = 0; + if (vid_mapping_table->entries[j].vid_7bit != 0) { + vid_mapping_table->entries[i] = + vid_mapping_table->entries[j]; + vid_mapping_table->entries[j].vid_7bit = 0; break; } } @@ -1492,7 +1493,7 @@ static void sumo_construct_vid_mapping_table(struct radeon_device *rdev, } }
- pi->sys_info.vid_mapping_table.num_entries = i; + vid_mapping_table->num_entries = i; }
union igp_info { @@ -1561,10 +1562,13 @@ static int sumo_parse_sys_info_table(struct radeon_device *rdev) else pi->sys_info.enable_boost = false; sumo_construct_display_voltage_mapping_table(rdev, + &pi->sys_info.disp_clk_voltage_mapping_table, igp_info->info_6.sDISPCLK_Voltage); sumo_construct_sclk_voltage_mapping_table(rdev, + &pi->sys_info.sclk_voltage_mapping_table, igp_info->info_6.sAvail_SCLK); - sumo_construct_vid_mapping_table(rdev, igp_info->info_6.sAvail_SCLK); + sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table, + igp_info->info_6.sAvail_SCLK);
} return 0; diff --git a/drivers/gpu/drm/radeon/sumo_dpm.h b/drivers/gpu/drm/radeon/sumo_dpm.h index 561bee1..d041a6c 100644 --- a/drivers/gpu/drm/radeon/sumo_dpm.h +++ b/drivers/gpu/drm/radeon/sumo_dpm.h @@ -23,6 +23,8 @@ #ifndef __SUMO_DPM_H__ #define __SUMO_DPM_H__
+#include "atom.h" + #define SUMO_MAX_HARDWARE_POWERLEVELS 5 #define SUMO_PM_NUMBER_OF_TC 15
@@ -184,7 +186,24 @@ struct sumo_power_info {
/* sumo_dpm.c */ u32 sumo_get_xclk(struct radeon_device *rdev); - +void sumo_gfx_clockgating_initialize(struct radeon_device *rdev); +void sumo_program_vc(struct radeon_device *rdev, u32 vrc); +void sumo_clear_vc(struct radeon_device *rdev); +void sumo_program_sstp(struct radeon_device *rdev); +void sumo_take_smu_control(struct radeon_device *rdev, bool enable); +void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev, + struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table, + ATOM_AVAILABLE_SCLK_LIST *table); +void sumo_construct_vid_mapping_table(struct radeon_device *rdev, + struct sumo_vid_mapping_table *vid_mapping_table, + ATOM_AVAILABLE_SCLK_LIST *table); +u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev, + struct sumo_vid_mapping_table *vid_mapping_table, + u32 vid_2bit); +u32 sumo_get_sleep_divider_from_id(u32 id); +u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev, + u32 sclk, + u32 min_sclk_in_sr);
/* sumo_smc.c */ void sumo_initialize_m3_arb(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/sumo_smc.c b/drivers/gpu/drm/radeon/sumo_smc.c index 9d0ae9b..bc1a510 100644 --- a/drivers/gpu/drm/radeon/sumo_smc.c +++ b/drivers/gpu/drm/radeon/sumo_smc.c @@ -21,13 +21,11 @@ * */
-#include <linux/firmware.h> #include "drmP.h" #include "radeon.h" #include "sumod.h" #include "sumo_dpm.h" #include "ppsmc.h" -#include "radeon_ucode.h"
#define SUMO_SMU_SERVICE_ROUTINE_PG_INIT 1 #define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY 27 diff --git a/drivers/gpu/drm/radeon/trinity_dpm.c b/drivers/gpu/drm/radeon/trinity_dpm.c new file mode 100644 index 0000000..c4779a6 --- /dev/null +++ b/drivers/gpu/drm/radeon/trinity_dpm.c @@ -0,0 +1,1613 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "radeon.h" +#include "trinityd.h" +#include "r600_dpm.h" +#include "trinity_dpm.h" + +#define TRINITY_MAX_DEEPSLEEP_DIVIDER_ID 5 +#define TRINITY_MINIMUM_ENGINE_CLOCK 800 +#define SCLK_MIN_DIV_INTV_SHIFT 12 +#define TRINITY_DISPCLK_BYPASS_THRESHOLD 10000 + +#ifndef TRINITY_MGCG_SEQUENCE +#define TRINITY_MGCG_SEQUENCE 100 + +static const u32 trinity_mgcg_shls_default[] = +{ + /* Register, Value, Mask */ + 0x0000802c, 0xc0000000, 0xffffffff, + 0x00003fc4, 0xc0000000, 0xffffffff, + 0x00005448, 0x00000100, 0xffffffff, + 0x000055e4, 0x00000100, 0xffffffff, + 0x0000160c, 0x00000100, 0xffffffff, + 0x00008984, 0x06000100, 0xffffffff, + 0x0000c164, 0x00000100, 0xffffffff, + 0x00008a18, 0x00000100, 0xffffffff, + 0x0000897c, 0x06000100, 0xffffffff, + 0x00008b28, 0x00000100, 0xffffffff, + 0x00009144, 0x00800200, 0xffffffff, + 0x00009a60, 0x00000100, 0xffffffff, + 0x00009868, 0x00000100, 0xffffffff, + 0x00008d58, 0x00000100, 0xffffffff, + 0x00009510, 0x00000100, 0xffffffff, + 0x0000949c, 0x00000100, 0xffffffff, + 0x00009654, 0x00000100, 0xffffffff, + 0x00009030, 0x00000100, 0xffffffff, + 0x00009034, 0x00000100, 0xffffffff, + 0x00009038, 0x00000100, 0xffffffff, + 0x0000903c, 0x00000100, 0xffffffff, + 0x00009040, 0x00000100, 0xffffffff, + 0x0000a200, 0x00000100, 0xffffffff, + 0x0000a204, 0x00000100, 0xffffffff, + 0x0000a208, 0x00000100, 0xffffffff, + 0x0000a20c, 0x00000100, 0xffffffff, + 0x00009744, 0x00000100, 0xffffffff, + 0x00003f80, 0x00000100, 0xffffffff, + 0x0000a210, 0x00000100, 0xffffffff, + 0x0000a214, 0x00000100, 0xffffffff, + 0x000004d8, 0x00000100, 0xffffffff, + 0x00009664, 0x00000100, 0xffffffff, + 0x00009698, 0x00000100, 0xffffffff, + 0x000004d4, 0x00000200, 0xffffffff, + 0x000004d0, 0x00000000, 0xffffffff, + 0x000030cc, 0x00000104, 0xffffffff, + 0x0000d0c0, 0x00000100, 0xffffffff, + 0x0000d8c0, 0x00000100, 0xffffffff, + 0x0000951c, 0x00010000, 0xffffffff, + 0x00009160, 0x00030002, 0xffffffff, + 0x00009164, 0x00050004, 0xffffffff, + 0x00009168, 0x00070006, 0xffffffff, + 0x00009178, 0x00070000, 0xffffffff, + 0x0000917c, 0x00030002, 0xffffffff, + 0x00009180, 0x00050004, 0xffffffff, + 0x0000918c, 0x00010006, 0xffffffff, + 0x00009190, 0x00090008, 0xffffffff, + 0x00009194, 0x00070000, 0xffffffff, + 0x00009198, 0x00030002, 0xffffffff, + 0x0000919c, 0x00050004, 0xffffffff, + 0x000091a8, 0x00010006, 0xffffffff, + 0x000091ac, 0x00090008, 0xffffffff, + 0x000091b0, 0x00070000, 0xffffffff, + 0x000091b4, 0x00030002, 0xffffffff, + 0x000091b8, 0x00050004, 0xffffffff, + 0x000091c4, 0x00010006, 0xffffffff, + 0x000091c8, 0x00090008, 0xffffffff, + 0x000091cc, 0x00070000, 0xffffffff, + 0x000091d0, 0x00030002, 0xffffffff, + 0x000091d4, 0x00050004, 0xffffffff, + 0x000091e0, 0x00010006, 0xffffffff, + 0x000091e4, 0x00090008, 0xffffffff, + 0x000091e8, 0x00000000, 0xffffffff, + 0x000091ec, 0x00070000, 0xffffffff, + 0x000091f0, 0x00030002, 0xffffffff, + 0x000091f4, 0x00050004, 0xffffffff, + 0x00009200, 0x00010006, 0xffffffff, + 0x00009204, 0x00090008, 0xffffffff, + 0x00009208, 0x00070000, 0xffffffff, + 0x0000920c, 0x00030002, 0xffffffff, + 0x00009210, 0x00050004, 0xffffffff, + 0x0000921c, 0x00010006, 0xffffffff, + 0x00009220, 0x00090008, 0xffffffff, + 0x00009294, 0x00000000, 0xffffffff +}; + +static const u32 trinity_mgcg_shls_enable[] = +{ + /* Register, Value, Mask */ + 0x0000802c, 0xc0000000, 0xffffffff, + 0x000008f8, 0x00000000, 0xffffffff, + 0x000008fc, 0x00000000, 0x000133FF, + 0x000008f8, 0x00000001, 0xffffffff, + 0x000008fc, 0x00000000, 0xE00B03FC, + 0x00009150, 0x96944200, 0xffffffff +}; + +static const u32 trinity_mgcg_shls_disable[] = +{ + /* Register, Value, Mask */ + 0x0000802c, 0xc0000000, 0xffffffff, + 0x00009150, 0x00600000, 0xffffffff, + 0x000008f8, 0x00000000, 0xffffffff, + 0x000008fc, 0xffffffff, 0x000133FF, + 0x000008f8, 0x00000001, 0xffffffff, + 0x000008fc, 0xffffffff, 0xE00B03FC +}; +#endif + +#ifndef TRINITY_SYSLS_SEQUENCE +#define TRINITY_SYSLS_SEQUENCE 100 + +static const u32 trinity_sysls_default[] = +{ + /* Register, Value, Mask */ + 0x000055e8, 0x00000000, 0xffffffff, + 0x0000d0bc, 0x00000000, 0xffffffff, + 0x0000d8bc, 0x00000000, 0xffffffff, + 0x000015c0, 0x000c1401, 0xffffffff, + 0x0000264c, 0x000c0400, 0xffffffff, + 0x00002648, 0x000c0400, 0xffffffff, + 0x00002650, 0x000c0400, 0xffffffff, + 0x000020b8, 0x000c0400, 0xffffffff, + 0x000020bc, 0x000c0400, 0xffffffff, + 0x000020c0, 0x000c0c80, 0xffffffff, + 0x0000f4a0, 0x000000c0, 0xffffffff, + 0x0000f4a4, 0x00680fff, 0xffffffff, + 0x00002f50, 0x00000404, 0xffffffff, + 0x000004c8, 0x00000001, 0xffffffff, + 0x0000641c, 0x00000000, 0xffffffff, + 0x00000c7c, 0x00000000, 0xffffffff, + 0x00006dfc, 0x00000000, 0xffffffff +}; + +static const u32 trinity_sysls_disable[] = +{ + /* Register, Value, Mask */ + 0x0000d0c0, 0x00000000, 0xffffffff, + 0x0000d8c0, 0x00000000, 0xffffffff, + 0x000055e8, 0x00000000, 0xffffffff, + 0x0000d0bc, 0x00000000, 0xffffffff, + 0x0000d8bc, 0x00000000, 0xffffffff, + 0x000015c0, 0x00041401, 0xffffffff, + 0x0000264c, 0x00040400, 0xffffffff, + 0x00002648, 0x00040400, 0xffffffff, + 0x00002650, 0x00040400, 0xffffffff, + 0x000020b8, 0x00040400, 0xffffffff, + 0x000020bc, 0x00040400, 0xffffffff, + 0x000020c0, 0x00040c80, 0xffffffff, + 0x0000f4a0, 0x000000c0, 0xffffffff, + 0x0000f4a4, 0x00680000, 0xffffffff, + 0x00002f50, 0x00000404, 0xffffffff, + 0x000004c8, 0x00000001, 0xffffffff, + 0x0000641c, 0x00007ffd, 0xffffffff, + 0x00000c7c, 0x0000ff00, 0xffffffff, + 0x00006dfc, 0x0000007f, 0xffffffff +}; + +static const u32 trinity_sysls_enable[] = +{ + /* Register, Value, Mask */ + 0x000055e8, 0x00000001, 0xffffffff, + 0x0000d0bc, 0x00000100, 0xffffffff, + 0x0000d8bc, 0x00000100, 0xffffffff, + 0x000015c0, 0x000c1401, 0xffffffff, + 0x0000264c, 0x000c0400, 0xffffffff, + 0x00002648, 0x000c0400, 0xffffffff, + 0x00002650, 0x000c0400, 0xffffffff, + 0x000020b8, 0x000c0400, 0xffffffff, + 0x000020bc, 0x000c0400, 0xffffffff, + 0x000020c0, 0x000c0c80, 0xffffffff, + 0x0000f4a0, 0x000000c0, 0xffffffff, + 0x0000f4a4, 0x00680fff, 0xffffffff, + 0x00002f50, 0x00000903, 0xffffffff, + 0x000004c8, 0x00000000, 0xffffffff, + 0x0000641c, 0x00000000, 0xffffffff, + 0x00000c7c, 0x00000000, 0xffffffff, + 0x00006dfc, 0x00000000, 0xffffffff +}; +#endif + +static const u32 trinity_override_mgpg_sequences[] = +{ + /* Register, Value */ + 0x00000200, 0xE030032C, + 0x00000204, 0x00000FFF, + 0x00000200, 0xE0300058, + 0x00000204, 0x00030301, + 0x00000200, 0xE0300054, + 0x00000204, 0x500010FF, + 0x00000200, 0xE0300074, + 0x00000204, 0x00030301, + 0x00000200, 0xE0300070, + 0x00000204, 0x500010FF, + 0x00000200, 0xE0300090, + 0x00000204, 0x00030301, + 0x00000200, 0xE030008C, + 0x00000204, 0x500010FF, + 0x00000200, 0xE03000AC, + 0x00000204, 0x00030301, + 0x00000200, 0xE03000A8, + 0x00000204, 0x500010FF, + 0x00000200, 0xE03000C8, + 0x00000204, 0x00030301, + 0x00000200, 0xE03000C4, + 0x00000204, 0x500010FF, + 0x00000200, 0xE03000E4, + 0x00000204, 0x00030301, + 0x00000200, 0xE03000E0, + 0x00000204, 0x500010FF, + 0x00000200, 0xE0300100, + 0x00000204, 0x00030301, + 0x00000200, 0xE03000FC, + 0x00000204, 0x500010FF, + 0x00000200, 0xE0300058, + 0x00000204, 0x00030303, + 0x00000200, 0xE0300054, + 0x00000204, 0x600010FF, + 0x00000200, 0xE0300074, + 0x00000204, 0x00030303, + 0x00000200, 0xE0300070, + 0x00000204, 0x600010FF, + 0x00000200, 0xE0300090, + 0x00000204, 0x00030303, + 0x00000200, 0xE030008C, + 0x00000204, 0x600010FF, + 0x00000200, 0xE03000AC, + 0x00000204, 0x00030303, + 0x00000200, 0xE03000A8, + 0x00000204, 0x600010FF, + 0x00000200, 0xE03000C8, + 0x00000204, 0x00030303, + 0x00000200, 0xE03000C4, + 0x00000204, 0x600010FF, + 0x00000200, 0xE03000E4, + 0x00000204, 0x00030303, + 0x00000200, 0xE03000E0, + 0x00000204, 0x600010FF, + 0x00000200, 0xE0300100, + 0x00000204, 0x00030303, + 0x00000200, 0xE03000FC, + 0x00000204, 0x600010FF, + 0x00000200, 0xE0300058, + 0x00000204, 0x00030303, + 0x00000200, 0xE0300054, + 0x00000204, 0x700010FF, + 0x00000200, 0xE0300074, + 0x00000204, 0x00030303, + 0x00000200, 0xE0300070, + 0x00000204, 0x700010FF, + 0x00000200, 0xE0300090, + 0x00000204, 0x00030303, + 0x00000200, 0xE030008C, + 0x00000204, 0x700010FF, + 0x00000200, 0xE03000AC, + 0x00000204, 0x00030303, + 0x00000200, 0xE03000A8, + 0x00000204, 0x700010FF, + 0x00000200, 0xE03000C8, + 0x00000204, 0x00030303, + 0x00000200, 0xE03000C4, + 0x00000204, 0x700010FF, + 0x00000200, 0xE03000E4, + 0x00000204, 0x00030303, + 0x00000200, 0xE03000E0, + 0x00000204, 0x700010FF, + 0x00000200, 0xE0300100, + 0x00000204, 0x00030303, + 0x00000200, 0xE03000FC, + 0x00000204, 0x700010FF, + 0x00000200, 0xE0300058, + 0x00000204, 0x00010303, + 0x00000200, 0xE0300054, + 0x00000204, 0x800010FF, + 0x00000200, 0xE0300074, + 0x00000204, 0x00010303, + 0x00000200, 0xE0300070, + 0x00000204, 0x800010FF, + 0x00000200, 0xE0300090, + 0x00000204, 0x00010303, + 0x00000200, 0xE030008C, + 0x00000204, 0x800010FF, + 0x00000200, 0xE03000AC, + 0x00000204, 0x00010303, + 0x00000200, 0xE03000A8, + 0x00000204, 0x800010FF, + 0x00000200, 0xE03000C4, + 0x00000204, 0x800010FF, + 0x00000200, 0xE03000C8, + 0x00000204, 0x00010303, + 0x00000200, 0xE03000E4, + 0x00000204, 0x00010303, + 0x00000200, 0xE03000E0, + 0x00000204, 0x800010FF, + 0x00000200, 0xE0300100, + 0x00000204, 0x00010303, + 0x00000200, 0xE03000FC, + 0x00000204, 0x800010FF, + 0x00000200, 0x0001f198, + 0x00000204, 0x0003ffff, + 0x00000200, 0x0001f19C, + 0x00000204, 0x3fffffff, + 0x00000200, 0xE030032C, + 0x00000204, 0x00000000, +}; + +static void trinity_program_clk_gating_hw_sequence(struct radeon_device *rdev, + const u32 *seq, u32 count); +static void trinity_override_dynamic_mg_powergating(struct radeon_device *rdev); +static void trinity_apply_state_adjust_rules(struct radeon_device *rdev); + +struct trinity_ps *trinity_get_ps(struct radeon_ps *rps) +{ + struct trinity_ps *ps = rps->ps_priv; + + return ps; +} + +struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = rdev->pm.dpm.priv; + + return pi; +} + +static void trinity_gfx_powergating_initialize(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + u32 p, u; + u32 value; + struct atom_clock_dividers dividers; + u32 xclk = sumo_get_xclk(rdev); + u32 sssd = 1; + int ret; + u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT; + + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + 25000, false, ÷rs); + if (ret) + return; + + value = RREG32_SMC(GFX_POWER_GATING_CNTL); + value &= ~(SSSD_MASK | PDS_DIV_MASK); + if (sssd) + value |= SSSD(1); + value |= PDS_DIV(dividers.post_div); + WREG32_SMC(GFX_POWER_GATING_CNTL, value); + + r600_calculate_u_and_p(500, xclk, 16, &p, &u); + + WREG32(CG_PG_CTRL, SP(p) | SU(u)); + + WREG32_P(CG_GIPOTS, CG_GIPOT(p), ~CG_GIPOT_MASK); + + /* XXX double check hw_rev */ + if (pi->override_dynamic_mgpg && (hw_rev == 0)) + trinity_override_dynamic_mg_powergating(rdev); + +} + +#define CGCG_CGTT_LOCAL0_MASK 0xFFFF33FF +#define CGCG_CGTT_LOCAL1_MASK 0xFFFB0FFE +#define CGTS_SM_CTRL_REG_DISABLE 0x00600000 +#define CGTS_SM_CTRL_REG_ENABLE 0x96944200 + +static void trinity_mg_clockgating_enable(struct radeon_device *rdev, + bool enable) +{ + u32 local0; + u32 local1; + + if (enable) { + local0 = RREG32_CG(CG_CGTT_LOCAL_0); + local1 = RREG32_CG(CG_CGTT_LOCAL_1); + + WREG32_CG(CG_CGTT_LOCAL_0, + (0x00380000 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); + WREG32_CG(CG_CGTT_LOCAL_1, + (0x0E000000 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); + + WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_ENABLE); + } else { + WREG32(CGTS_SM_CTRL_REG, CGTS_SM_CTRL_REG_DISABLE); + + local0 = RREG32_CG(CG_CGTT_LOCAL_0); + local1 = RREG32_CG(CG_CGTT_LOCAL_1); + + WREG32_CG(CG_CGTT_LOCAL_0, + CGCG_CGTT_LOCAL0_MASK | (local0 & ~CGCG_CGTT_LOCAL0_MASK) ); + WREG32_CG(CG_CGTT_LOCAL_1, + CGCG_CGTT_LOCAL1_MASK | (local1 & ~CGCG_CGTT_LOCAL1_MASK) ); + } +} + +static void trinity_mg_clockgating_initialize(struct radeon_device *rdev) +{ + u32 count; + const u32 *seq = NULL; + + seq = &trinity_mgcg_shls_default[0]; + count = sizeof(trinity_mgcg_shls_default) / (3 * sizeof(u32)); + + trinity_program_clk_gating_hw_sequence(rdev, seq, count); +} + +static void trinity_gfx_clockgating_enable(struct radeon_device *rdev, + bool enable) +{ + if (enable) { + WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); + } else { + WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); + WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); + WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); + RREG32(GB_ADDR_CONFIG); + } +} + +static void trinity_program_clk_gating_hw_sequence(struct radeon_device *rdev, + const u32 *seq, u32 count) +{ + u32 i, length = count * 3; + + for (i = 0; i < length; i += 3) + WREG32_P(seq[i], seq[i+1], ~seq[i+2]); +} + +static void trinity_program_override_mgpg_sequences(struct radeon_device *rdev, + const u32 *seq, u32 count) +{ + u32 i, length = count * 2; + + for (i = 0; i < length; i += 2) + WREG32(seq[i], seq[i+1]); + +} + +static void trinity_override_dynamic_mg_powergating(struct radeon_device *rdev) +{ + u32 count; + const u32 *seq = NULL; + + seq = &trinity_override_mgpg_sequences[0]; + count = sizeof(trinity_override_mgpg_sequences) / (2 * sizeof(u32)); + + trinity_program_override_mgpg_sequences(rdev, seq, count); +} + +static void trinity_ls_clockgating_enable(struct radeon_device *rdev, + bool enable) +{ + u32 count; + const u32 *seq = NULL; + + if (enable) { + seq = &trinity_sysls_enable[0]; + count = sizeof(trinity_sysls_enable) / (3 * sizeof(u32)); + } else { + seq = &trinity_sysls_disable[0]; + count = sizeof(trinity_sysls_disable) / (3 * sizeof(u32)); + } + + trinity_program_clk_gating_hw_sequence(rdev, seq, count); +} + +static void trinity_gfx_powergating_enable(struct radeon_device *rdev, + bool enable) +{ + if (enable) { + if (RREG32_SMC(CC_SMU_TST_EFUSE1_MISC) & RB_BACKEND_DISABLE_MASK) + WREG32_SMC(SMU_SCRATCH_A, (RREG32_SMC(SMU_SCRATCH_A) | 0x01)); + + WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); + } else { + WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN); + RREG32(GB_ADDR_CONFIG); + } +} + +static void trinity_gfx_dynamic_mgpg_enable(struct radeon_device *rdev, + bool enable) +{ + u32 value; + + if (enable) { + value = RREG32_SMC(PM_I_CNTL_1); + value &= ~DS_PG_CNTL_MASK; + value |= DS_PG_CNTL(1); + WREG32_SMC(PM_I_CNTL_1, value); + + value = RREG32_SMC(SMU_S_PG_CNTL); + value &= ~DS_PG_EN_MASK; + value |= DS_PG_EN(1); + WREG32_SMC(SMU_S_PG_CNTL, value); + } else { + value = RREG32_SMC(SMU_S_PG_CNTL); + value &= ~DS_PG_EN_MASK; + WREG32_SMC(SMU_S_PG_CNTL, value); + + value = RREG32_SMC(PM_I_CNTL_1); + value &= ~DS_PG_CNTL_MASK; + WREG32_SMC(PM_I_CNTL_1, value); + } + + trinity_gfx_dynamic_mgpg_config(rdev); + +} + +static void trinity_enable_clock_power_gating(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + if (pi->enable_gfx_clock_gating) + sumo_gfx_clockgating_initialize(rdev); + if (pi->enable_mg_clock_gating) + trinity_mg_clockgating_initialize(rdev); + if (pi->enable_gfx_power_gating) + trinity_gfx_powergating_initialize(rdev); + if (pi->enable_mg_clock_gating) { + trinity_ls_clockgating_enable(rdev, true); + trinity_mg_clockgating_enable(rdev, true); + } + if (pi->enable_gfx_clock_gating) + trinity_gfx_clockgating_enable(rdev, true); + if (pi->enable_gfx_dynamic_mgpg) + trinity_gfx_dynamic_mgpg_enable(rdev, true); + if (pi->enable_gfx_power_gating) + trinity_gfx_powergating_enable(rdev, true); +} + +static void trinity_disable_clock_power_gating(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + if (pi->enable_gfx_power_gating) + trinity_gfx_powergating_enable(rdev, false); + if (pi->enable_gfx_dynamic_mgpg) + trinity_gfx_dynamic_mgpg_enable(rdev, false); + if (pi->enable_gfx_clock_gating) + trinity_gfx_clockgating_enable(rdev, false); + if (pi->enable_mg_clock_gating) { + trinity_mg_clockgating_enable(rdev, false); + trinity_ls_clockgating_enable(rdev, false); + } +} + +static void trinity_set_divider_value(struct radeon_device *rdev, + u32 index, u32 sclk) +{ + struct atom_clock_dividers dividers; + int ret; + u32 value; + u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; + + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + sclk, false, ÷rs); + if (ret) + return; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); + value &= ~CLK_DIVIDER_MASK; + value |= CLK_DIVIDER(dividers.post_div); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); + + ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, + sclk/2, false, ÷rs); + if (ret) + return; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix); + value &= ~PD_SCLK_DIVIDER_MASK; + value |= PD_SCLK_DIVIDER(dividers.post_div); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_PG_CNTL + ix, value); +} + +static void trinity_set_ds_dividers(struct radeon_device *rdev, + u32 index, u32 divider) +{ + u32 value; + u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); + value &= ~DS_DIV_MASK; + value |= DS_DIV(divider); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); +} + +static void trinity_set_ss_dividers(struct radeon_device *rdev, + u32 index, u32 divider) +{ + u32 value; + u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); + value &= ~DS_SH_DIV_MASK; + value |= DS_SH_DIV(divider); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); +} + +static void trinity_set_vid(struct radeon_device *rdev, u32 index, u32 vid) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid); + u32 value; + u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); + value &= ~VID_MASK; + value |= VID(vid_7bit); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); + value &= ~LVRT_MASK; + value |= LVRT(0); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); +} + +static void trinity_set_allos_gnb_slow(struct radeon_device *rdev, + u32 index, u32 gnb_slow) +{ + u32 value; + u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix); + value &= ~GNB_SLOW_MASK; + value |= GNB_SLOW(gnb_slow); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value); +} + +static void trinity_set_force_nbp_state(struct radeon_device *rdev, + u32 index, u32 force_nbp_state) +{ + u32 value; + u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix); + value &= ~FORCE_NBPS1_MASK; + value |= FORCE_NBPS1(force_nbp_state); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_3 + ix, value); +} + +static void trinity_set_display_wm(struct radeon_device *rdev, + u32 index, u32 wm) +{ + u32 value; + u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); + value &= ~DISPLAY_WM_MASK; + value |= DISPLAY_WM(wm); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); +} + +static void trinity_set_vce_wm(struct radeon_device *rdev, + u32 index, u32 wm) +{ + u32 value; + u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); + value &= ~VCE_WM_MASK; + value |= VCE_WM(wm); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); +} + +static void trinity_set_at(struct radeon_device *rdev, + u32 index, u32 at) +{ + u32 value; + u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix); + value &= ~AT_MASK; + value |= AT(at); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value); +} + +static void trinity_program_power_level(struct radeon_device *rdev, + struct trinity_pl *pl, u32 index) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + if (index >= SUMO_MAX_HARDWARE_POWERLEVELS) + return; + + trinity_set_divider_value(rdev, index, pl->sclk); + trinity_set_vid(rdev, index, pl->vddc_index); + trinity_set_ss_dividers(rdev, index, pl->ss_divider_index); + trinity_set_ds_dividers(rdev, index, pl->ds_divider_index); + trinity_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow); + trinity_set_force_nbp_state(rdev, index, pl->force_nbp_state); + trinity_set_display_wm(rdev, index, pl->display_wm); + trinity_set_vce_wm(rdev, index, pl->vce_wm); + trinity_set_at(rdev, index, pi->at[index]); +} + +static void trinity_power_level_enable_disable(struct radeon_device *rdev, + u32 index, bool enable) +{ + u32 value; + u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; + + value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix); + value &= ~STATE_VALID_MASK; + if (enable) + value |= STATE_VALID(1); + WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_0 + ix, value); +} + +static bool trinity_dpm_enabled(struct radeon_device *rdev) +{ + if (RREG32_SMC(SMU_SCLK_DPM_CNTL) & SCLK_DPM_EN(1)) + return true; + else + return false; +} + +static void trinity_start_dpm(struct radeon_device *rdev) +{ + u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL); + + value &= ~(SCLK_DPM_EN_MASK | SCLK_DPM_BOOT_STATE_MASK | VOLTAGE_CHG_EN_MASK); + value |= SCLK_DPM_EN(1) | SCLK_DPM_BOOT_STATE(0) | VOLTAGE_CHG_EN(1); + WREG32_SMC(SMU_SCLK_DPM_CNTL, value); + + WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); + WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~EN); + + trinity_dpm_config(rdev, true); +} + +static void trinity_wait_for_dpm_enabled(struct radeon_device *rdev) +{ + int i; + + for (i = 0; i < rdev->usec_timeout; i++) { + if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN) + break; + udelay(1); + } + for (i = 0; i < rdev->usec_timeout; i++) { + if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & TARGET_STATE_MASK) == 0) + break; + udelay(1); + } + for (i = 0; i < rdev->usec_timeout; i++) { + if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0) + break; + udelay(1); + } +} + +static void trinity_stop_dpm(struct radeon_device *rdev) +{ + u32 sclk_dpm_cntl; + + WREG32_P(CG_CG_VOLTAGE_CNTL, EN, ~EN); + + sclk_dpm_cntl = RREG32_SMC(SMU_SCLK_DPM_CNTL); + sclk_dpm_cntl &= ~(SCLK_DPM_EN_MASK | VOLTAGE_CHG_EN_MASK); + WREG32_SMC(SMU_SCLK_DPM_CNTL, sclk_dpm_cntl); + + trinity_dpm_config(rdev, false); +} + +static void trinity_start_am(struct radeon_device *rdev) +{ + WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT)); +} + +static void trinity_reset_am(struct radeon_device *rdev) +{ + WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT, + ~(RESET_SCLK_CNT | RESET_BUSY_CNT)); +} + +static void trinity_wait_for_level_0(struct radeon_device *rdev) +{ + int i; + + for (i = 0; i < rdev->usec_timeout; i++) { + if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_MASK) == 0) + break; + udelay(1); + } +} + +static void trinity_enable_power_level_0(struct radeon_device *rdev) +{ + trinity_power_level_enable_disable(rdev, 0, true); +} + +static void trinity_force_level_0(struct radeon_device *rdev) +{ + trinity_dpm_force_state(rdev, 0); +} + +static void trinity_unforce_levels(struct radeon_device *rdev) +{ + trinity_dpm_no_forced_level(rdev); +} + +static void trinity_update_current_power_levels(struct radeon_device *rdev) +{ + struct trinity_ps *new_ps = trinity_get_ps(rdev->pm.dpm.requested_ps); + struct trinity_power_info *pi = trinity_get_pi(rdev); + + pi->current_ps = *new_ps; +} + +static void trinity_program_power_levels_0_to_n(struct radeon_device *rdev) +{ + struct trinity_ps *new_ps = trinity_get_ps(rdev->pm.dpm.requested_ps); + struct trinity_ps *old_ps = trinity_get_ps(rdev->pm.dpm.current_ps); + u32 i; + u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; + + for (i = 0; i < new_ps->num_levels; i++) { + trinity_program_power_level(rdev, &new_ps->levels[i], i); + trinity_power_level_enable_disable(rdev, i, true); + } + + for (i = new_ps->num_levels; i < n_current_state_levels; i++) + trinity_power_level_enable_disable(rdev, i, false); +} + +static void trinity_program_bootup_state(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + u32 i; + + trinity_program_power_level(rdev, &pi->boot_pl, 0); + trinity_power_level_enable_disable(rdev, 0, true); + + for (i = 1; i < 8; i++) + trinity_power_level_enable_disable(rdev, i, false); +} + +static void trinity_program_ttt(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT); + + value &= ~(HT_MASK | LT_MASK); + value |= HT((pi->thermal_auto_throttling + 49) * 8); + value |= LT((pi->thermal_auto_throttling + 49 - pi->sys_info.htc_hyst_lmt) * 8); + WREG32_SMC(SMU_SCLK_DPM_TTT, value); +} + +static void trinity_enable_att(struct radeon_device *rdev) +{ + u32 value = RREG32_SMC(SMU_SCLK_DPM_TT_CNTL); + + value &= ~SCLK_TT_EN_MASK; + value |= SCLK_TT_EN(1); + WREG32_SMC(SMU_SCLK_DPM_TT_CNTL, value); +} + +static void trinity_program_sclk_dpm(struct radeon_device *rdev) +{ + u32 p, u; + u32 tp = RREG32_SMC(PM_TP); + u32 ni; + u32 xclk = sumo_get_xclk(rdev); + u32 value; + + r600_calculate_u_and_p(400, xclk, 16, &p, &u); + + ni = (p + tp - 1) / tp; + + value = RREG32_SMC(PM_I_CNTL_1); + value &= ~SCLK_DPM_MASK; + value |= SCLK_DPM(ni); + WREG32_SMC(PM_I_CNTL_1, value); +} + +static int trinity_set_thermal_temperature_range(struct radeon_device *rdev, + int min_temp, int max_temp) +{ + int low_temp = 0 * 1000; + int high_temp = 255 * 1000; + + if (low_temp < min_temp) + low_temp = min_temp; + if (high_temp > max_temp) + high_temp = max_temp; + if (high_temp < low_temp) { + DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); + return -EINVAL; + } + + WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK); + WREG32_P(CG_THERMAL_INT_CTRL, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK); + + rdev->pm.dpm.thermal.min_temp = low_temp; + rdev->pm.dpm.thermal.max_temp = high_temp; + + return 0; +} + +int trinity_dpm_enable(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + trinity_acquire_mutex(rdev); + + if (trinity_dpm_enabled(rdev)) { + trinity_release_mutex(rdev); + return -EINVAL; + } + + trinity_enable_clock_power_gating(rdev); + trinity_program_bootup_state(rdev); + sumo_program_vc(rdev, 0x00C00033); + trinity_start_am(rdev); + if (pi->enable_auto_thermal_throttling) { + trinity_program_ttt(rdev); + trinity_enable_att(rdev); + } + trinity_program_sclk_dpm(rdev); + trinity_start_dpm(rdev); + trinity_wait_for_dpm_enabled(rdev); + trinity_release_mutex(rdev); + + if (rdev->irq.installed && + r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { + trinity_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); + rdev->irq.dpm_thermal = true; + radeon_irq_set(rdev); + } + + return 0; +} + +void trinity_dpm_disable(struct radeon_device *rdev) +{ + trinity_acquire_mutex(rdev); + if (!trinity_dpm_enabled(rdev)) { + trinity_release_mutex(rdev); + return; + } + trinity_disable_clock_power_gating(rdev); + sumo_clear_vc(rdev); + trinity_wait_for_level_0(rdev); + trinity_stop_dpm(rdev); + trinity_reset_am(rdev); + trinity_release_mutex(rdev); + + if (rdev->irq.installed && + r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) { + rdev->irq.dpm_thermal = false; + radeon_irq_set(rdev); + } +} + +static void trinity_get_min_sclk_divider(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + pi->min_sclk_did = + (RREG32_SMC(CC_SMU_MISC_FUSES) & MinSClkDid_MASK) >> MinSClkDid_SHIFT; +} + +static void trinity_setup_nbp_sim(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + struct trinity_ps *new_ps = trinity_get_ps(rdev->pm.dpm.requested_ps); + u32 nbpsconfig; + + if (pi->sys_info.nb_dpm_enable) { + nbpsconfig = RREG32_SMC(NB_PSTATE_CONFIG); + nbpsconfig &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK | DpmXNbPsLo_MASK | DpmXNbPsHi_MASK); + nbpsconfig |= (Dpm0PgNbPsLo(new_ps->Dpm0PgNbPsLo) | + Dpm0PgNbPsHi(new_ps->Dpm0PgNbPsHi) | + DpmXNbPsLo(new_ps->DpmXNbPsLo) | + DpmXNbPsHi(new_ps->DpmXNbPsHi)); + WREG32_SMC(NB_PSTATE_CONFIG, nbpsconfig); + } +} + +int trinity_dpm_set_power_state(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + trinity_apply_state_adjust_rules(rdev); + trinity_update_current_power_levels(rdev); + + trinity_acquire_mutex(rdev); + if (pi->enable_dpm) { + trinity_enable_power_level_0(rdev); + trinity_force_level_0(rdev); + trinity_wait_for_level_0(rdev); + trinity_setup_nbp_sim(rdev); + trinity_program_power_levels_0_to_n(rdev); + trinity_force_level_0(rdev); + trinity_unforce_levels(rdev); + } + trinity_release_mutex(rdev); + + return 0; +} + +void trinity_dpm_setup_asic(struct radeon_device *rdev) +{ + trinity_acquire_mutex(rdev); + sumo_program_sstp(rdev); + sumo_take_smu_control(rdev, true); + trinity_get_min_sclk_divider(rdev); + trinity_release_mutex(rdev); +} + +void trinity_dpm_reset_asic(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + trinity_acquire_mutex(rdev); + if (pi->enable_dpm) { + trinity_enable_power_level_0(rdev); + trinity_force_level_0(rdev); + trinity_wait_for_level_0(rdev); + trinity_program_bootup_state(rdev); + trinity_force_level_0(rdev); + trinity_unforce_levels(rdev); + } + trinity_release_mutex(rdev); +} + +static u16 trinity_convert_voltage_index_to_value(struct radeon_device *rdev, + u32 vid_2bit) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit); + u32 svi_mode = (RREG32_SMC(PM_CONFIG) & SVI_Mode) ? 1 : 0; + u32 step = (svi_mode == 0) ? 1250 : 625; + u32 delta = vid_7bit * step + 50; + + if (delta > 155000) + return 0; + + return (155000 - delta) / 100; +} + +static void trinity_patch_boot_state(struct radeon_device *rdev, + struct trinity_ps *ps) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + ps->num_levels = 1; + ps->nbps_flags = 0; + ps->bapm_flags = 0; + ps->levels[0] = pi->boot_pl; +} + +static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) +{ + if (sclk < 20000) + return 1; + return 0; +} + +static void trinity_construct_boot_state(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + pi->boot_pl.sclk = pi->sys_info.bootup_sclk; + pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index; + pi->boot_pl.ds_divider_index = 0; + pi->boot_pl.ss_divider_index = 0; + pi->boot_pl.allow_gnb_slow = 1; + pi->boot_pl.force_nbp_state = 0; + pi->boot_pl.display_wm = 0; + pi->boot_pl.vce_wm = 0; + pi->current_ps.num_levels = 1; + pi->current_ps.levels[0] = pi->boot_pl; +} + +static u8 trinity_get_sleep_divider_id_from_clock(struct radeon_device *rdev, + u32 sclk, u32 min_sclk_in_sr) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + u32 i; + u32 temp; + u32 min = (min_sclk_in_sr > TRINITY_MINIMUM_ENGINE_CLOCK) ? + min_sclk_in_sr : TRINITY_MINIMUM_ENGINE_CLOCK; + + if (sclk < min) + return 0; + + if (!pi->enable_sclk_ds) + return 0; + + for (i = TRINITY_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { + temp = sclk / sumo_get_sleep_divider_from_id(i); + if (temp >= min || i == 0) + break; + } + + return (u8)i; +} + +static u32 trinity_get_valid_engine_clock(struct radeon_device *rdev, + u32 lower_limit) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + u32 i; + + for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) { + if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit) + return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency; + } + + if (i == pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries) + DRM_ERROR("engine clock out of range!"); + + return 0; +} + +static void trinity_patch_thermal_state(struct radeon_device *rdev, + struct trinity_ps *ps, + struct trinity_ps *current_ps) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ + u32 current_vddc; + u32 current_sclk; + u32 current_index = 0; + + if (current_ps) { + current_vddc = current_ps->levels[current_index].vddc_index; + current_sclk = current_ps->levels[current_index].sclk; + } else { + current_vddc = pi->boot_pl.vddc_index; + current_sclk = pi->boot_pl.sclk; + } + + ps->levels[0].vddc_index = current_vddc; + + if (ps->levels[0].sclk > current_sclk) + ps->levels[0].sclk = current_sclk; + + ps->levels[0].ds_divider_index = + trinity_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr); + ps->levels[0].ss_divider_index = ps->levels[0].ds_divider_index; + ps->levels[0].allow_gnb_slow = 1; + ps->levels[0].force_nbp_state = 0; + ps->levels[0].display_wm = 0; + ps->levels[0].vce_wm = + trinity_calculate_vce_wm(rdev, ps->levels[0].sclk); +} + +static u8 trinity_calculate_display_wm(struct radeon_device *rdev, + struct trinity_ps *ps, u32 index) +{ + if (ps == NULL || ps->num_levels <= 1) + return 0; + else if (ps->num_levels == 2) { + if (index == 0) + return 0; + else + return 1; + } else { + if (index == 0) + return 0; + else if (ps->levels[index].sclk < 30000) + return 0; + else + return 1; + } +} + +static void trinity_apply_state_adjust_rules(struct radeon_device *rdev) +{ + struct radeon_ps *rps = rdev->pm.dpm.requested_ps; + struct trinity_ps *ps = trinity_get_ps(rps); + struct trinity_ps *current_ps = trinity_get_ps(rdev->pm.dpm.current_ps); + struct trinity_power_info *pi = trinity_get_pi(rdev); + u32 min_voltage = 0; /* ??? */ + u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */ + u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */ + u32 i; + bool force_high; + u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; + + if (rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) + return trinity_patch_thermal_state(rdev, ps, current_ps); + + for (i = 0; i < ps->num_levels; i++) { + if (ps->levels[i].vddc_index < min_voltage) + ps->levels[i].vddc_index = min_voltage; + + if (ps->levels[i].sclk < min_sclk) + ps->levels[i].sclk = + trinity_get_valid_engine_clock(rdev, min_sclk); + + ps->levels[i].ds_divider_index = + sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr); + + ps->levels[i].ss_divider_index = ps->levels[i].ds_divider_index; + + ps->levels[i].allow_gnb_slow = 1; + ps->levels[i].force_nbp_state = 0; + ps->levels[i].display_wm = + trinity_calculate_display_wm(rdev, ps, i); + ps->levels[i].vce_wm = + trinity_calculate_vce_wm(rdev, ps->levels[0].sclk); + } + + if ((rps->class & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) || + ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)) + ps->bapm_flags |= TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE; + + if (pi->sys_info.nb_dpm_enable) { + ps->Dpm0PgNbPsLo = 0x1; + ps->Dpm0PgNbPsHi = 0x0; + ps->DpmXNbPsLo = 0x2; + ps->DpmXNbPsHi = 0x1; + + if ((rps->class & (ATOM_PPLIB_CLASSIFICATION_HDSTATE | ATOM_PPLIB_CLASSIFICATION_SDSTATE)) || + ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)) { + force_high = ((rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) || + ((rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) && + (pi->sys_info.uma_channel_number == 1))); + force_high = (num_active_displays >= 3) || force_high; + ps->Dpm0PgNbPsLo = force_high ? 0x2 : 0x3; + ps->Dpm0PgNbPsHi = 0x1; + ps->DpmXNbPsLo = force_high ? 0x2 : 0x3; + ps->DpmXNbPsHi = 0x2; + ps->levels[ps->num_levels - 1].allow_gnb_slow = 0; + } + } +} + +static void trinity_cleanup_asic(struct radeon_device *rdev) +{ + sumo_take_smu_control(rdev, false); +} + +#if 0 +static void trinity_pre_display_configuration_change(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + if (pi->voltage_drop_in_dce) + trinity_dce_enable_voltage_adjustment(rdev, false); +} +#endif + +static void trinity_add_dccac_value(struct radeon_device *rdev) +{ + u32 gpu_cac_avrg_cntl_window_size; + u32 num_active_displays = rdev->pm.dpm.new_active_crtc_count; + u64 disp_clk = rdev->clock.default_dispclk / 100; + u32 dc_cac_value; + + gpu_cac_avrg_cntl_window_size = + (RREG32_SMC(GPU_CAC_AVRG_CNTL) & WINDOW_SIZE_MASK) >> WINDOW_SIZE_SHIFT; + + dc_cac_value = (u32)((14213 * disp_clk * disp_clk * (u64)num_active_displays) >> + (32 - gpu_cac_avrg_cntl_window_size)); + + WREG32_SMC(DC_CAC_VALUE, dc_cac_value); +} + +void trinity_dpm_display_configuration_changed(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + if (pi->voltage_drop_in_dce) + trinity_dce_enable_voltage_adjustment(rdev, true); + trinity_add_dccac_value(rdev); +} + +union power_info { + struct _ATOM_POWERPLAY_INFO info; + struct _ATOM_POWERPLAY_INFO_V2 info_2; + struct _ATOM_POWERPLAY_INFO_V3 info_3; + struct _ATOM_PPLIB_POWERPLAYTABLE pplib; + struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; + struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; +}; + +union pplib_clock_info { + struct _ATOM_PPLIB_R600_CLOCK_INFO r600; + struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; + struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; + struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; +}; + +union pplib_power_state { + struct _ATOM_PPLIB_STATE v1; + struct _ATOM_PPLIB_STATE_V2 v2; +}; + +static void trinity_parse_pplib_non_clock_info(struct radeon_device *rdev, + struct radeon_ps *rps, + struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, + u8 table_rev) +{ + struct trinity_ps *ps = trinity_get_ps(rps); + + rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); + rps->class = le16_to_cpu(non_clock_info->usClassification); + rps->class2 = le16_to_cpu(non_clock_info->usClassification2); + + if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { + rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); + rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); + } else { + rps->vclk = 0; + rps->dclk = 0; + } + + if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { + rdev->pm.dpm.boot_ps = rps; + trinity_patch_boot_state(rdev, ps); + } + if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) + rdev->pm.dpm.uvd_ps = rps; +} + +static void trinity_parse_pplib_clock_info(struct radeon_device *rdev, + struct radeon_ps *rps, int index, + union pplib_clock_info *clock_info) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + struct trinity_ps *ps = trinity_get_ps(rps); + struct trinity_pl *pl = &ps->levels[index]; + u32 sclk; + + sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow); + sclk |= clock_info->sumo.ucEngineClockHigh << 16; + pl->sclk = sclk; + pl->vddc_index = clock_info->sumo.vddcIndex; + + ps->num_levels = index + 1; + + if (pi->enable_sclk_ds) { + pl->ds_divider_index = 5; + pl->ss_divider_index = 5; + } +} + +static int trinity_parse_power_table(struct radeon_device *rdev) +{ + struct radeon_mode_info *mode_info = &rdev->mode_info; + struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; + union pplib_power_state *power_state; + int i, j, k, non_clock_array_index, clock_array_index; + union pplib_clock_info *clock_info; + struct _StateArray *state_array; + struct _ClockInfoArray *clock_info_array; + struct _NonClockInfoArray *non_clock_info_array; + union power_info *power_info; + int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); + u16 data_offset; + u8 frev, crev; + u8 *power_state_offset; + struct sumo_ps *ps; + + if (!atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) + return -EINVAL; + power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); + + state_array = (struct _StateArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usStateArrayOffset)); + clock_info_array = (struct _ClockInfoArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); + non_clock_info_array = (struct _NonClockInfoArray *) + (mode_info->atom_context->bios + data_offset + + le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); + + rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) * + state_array->ucNumEntries, GFP_KERNEL); + if (!rdev->pm.dpm.ps) + return -ENOMEM; + power_state_offset = (u8 *)state_array->states; + rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps); + rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime); + rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime); + for (i = 0; i < state_array->ucNumEntries; i++) { + power_state = (union pplib_power_state *)power_state_offset; + non_clock_array_index = power_state->v2.nonClockInfoIndex; + non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) + &non_clock_info_array->nonClockInfo[non_clock_array_index]; + if (!rdev->pm.power_state[i].clock_info) + return -EINVAL; + ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL); + if (ps == NULL) { + kfree(rdev->pm.dpm.ps); + return -ENOMEM; + } + rdev->pm.dpm.ps[i].ps_priv = ps; + k = 0; + for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { + clock_array_index = power_state->v2.clockInfoIndex[j]; + if (clock_array_index >= clock_info_array->ucNumEntries) + continue; + if (k >= SUMO_MAX_HARDWARE_POWERLEVELS) + break; + clock_info = (union pplib_clock_info *) + &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; + trinity_parse_pplib_clock_info(rdev, + &rdev->pm.dpm.ps[i], k, + clock_info); + k++; + } + trinity_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], + non_clock_info, + non_clock_info_array->ucEntrySize); + power_state_offset += 2 + power_state->v2.ucNumDPMLevels; + } + rdev->pm.dpm.num_ps = state_array->ucNumEntries; + return 0; +} + +union igp_info { + struct _ATOM_INTEGRATED_SYSTEM_INFO info; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; + struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; +}; + +static int trinity_parse_sys_info_table(struct radeon_device *rdev) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + struct radeon_mode_info *mode_info = &rdev->mode_info; + int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); + union igp_info *igp_info; + u8 frev, crev; + u16 data_offset; + int i; + + if (atom_parse_data_header(mode_info->atom_context, index, NULL, + &frev, &crev, &data_offset)) { + igp_info = (union igp_info *)(mode_info->atom_context->bios + + data_offset); + + if (crev != 7) { + DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); + return -EINVAL; + } + pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_7.ulBootUpEngineClock); + pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_7.ulMinEngineClock); + pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_7.ulBootUpUMAClock); + pi->sys_info.bootup_nb_voltage_index = + le16_to_cpu(igp_info->info_7.usBootUpNBVoltage); + if (igp_info->info_7.ucHtcTmpLmt == 0) + pi->sys_info.htc_tmp_lmt = 203; + else + pi->sys_info.htc_tmp_lmt = igp_info->info_7.ucHtcTmpLmt; + if (igp_info->info_7.ucHtcHystLmt == 0) + pi->sys_info.htc_hyst_lmt = 5; + else + pi->sys_info.htc_hyst_lmt = igp_info->info_7.ucHtcHystLmt; + if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) { + DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n"); + } + + if (pi->enable_nbps_policy) + pi->sys_info.nb_dpm_enable = igp_info->info_7.ucNBDPMEnable; + else + pi->sys_info.nb_dpm_enable = 0; + + for (i = 0; i < TRINITY_NUM_NBPSTATES; i++) { + pi->sys_info.nbp_mclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateMemclkFreq[i]); + pi->sys_info.nbp_nclk[i] = le32_to_cpu(igp_info->info_7.ulNbpStateNClkFreq[i]); + } + + pi->sys_info.nbp_voltage_index[0] = le16_to_cpu(igp_info->info_7.usNBP0Voltage); + pi->sys_info.nbp_voltage_index[1] = le16_to_cpu(igp_info->info_7.usNBP1Voltage); + pi->sys_info.nbp_voltage_index[2] = le16_to_cpu(igp_info->info_7.usNBP2Voltage); + pi->sys_info.nbp_voltage_index[3] = le16_to_cpu(igp_info->info_7.usNBP3Voltage); + + if (!pi->sys_info.nb_dpm_enable) { + for (i = 1; i < TRINITY_NUM_NBPSTATES; i++) { + pi->sys_info.nbp_mclk[i] = pi->sys_info.nbp_mclk[0]; + pi->sys_info.nbp_nclk[i] = pi->sys_info.nbp_nclk[0]; + pi->sys_info.nbp_voltage_index[i] = pi->sys_info.nbp_voltage_index[0]; + } + } + + pi->sys_info.uma_channel_number = igp_info->info_7.ucUMAChannelNumber; + + sumo_construct_sclk_voltage_mapping_table(rdev, + &pi->sys_info.sclk_voltage_mapping_table, + igp_info->info_7.sAvail_SCLK); + sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table, + igp_info->info_7.sAvail_SCLK); + + } + return 0; +} + +int trinity_dpm_init(struct radeon_device *rdev) +{ + struct trinity_power_info *pi; + int ret, i; + + pi = kzalloc(sizeof(struct trinity_power_info), GFP_KERNEL); + if (pi == NULL) + return -ENOMEM; + rdev->pm.dpm.priv = pi; + + for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) + pi->at[i] = TRINITY_AT_DFLT; + + pi->enable_nbps_policy = true; + pi->enable_sclk_ds = true; + pi->enable_gfx_power_gating = true; + pi->enable_gfx_clock_gating = true; + pi->enable_mg_clock_gating = true; + pi->enable_gfx_dynamic_mgpg = true; /* ??? */ + pi->override_dynamic_mgpg = true; + pi->enable_auto_thermal_throttling = true; + pi->voltage_drop_in_dce = false; /* need to restructure dpm/modeset interaction */ + + ret = trinity_parse_sys_info_table(rdev); + if (ret) + return ret; + + trinity_construct_boot_state(rdev); + + ret = trinity_parse_power_table(rdev); + if (ret) + return ret; + + pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt; + pi->enable_dpm = true; + + return 0; +} + +void trinity_dpm_print_power_state(struct radeon_device *rdev, + struct radeon_ps *rps) +{ + int i; + struct trinity_ps *ps = trinity_get_ps(rps); + + r600_dpm_print_class_info(rps->class, rps->class2); + r600_dpm_print_cap_info(rps->caps); + printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); + for (i = 0; i < ps->num_levels; i++) { + struct trinity_pl *pl = &ps->levels[i]; + printk("\t\tpower level %d sclk: %u vddc: %u\n", + i, pl->sclk, + trinity_convert_voltage_index_to_value(rdev, pl->vddc_index)); + } + r600_dpm_print_ps_status(rdev, rps); +} + +void trinity_dpm_fini(struct radeon_device *rdev) +{ + int i; + + trinity_cleanup_asic(rdev); /* ??? */ + + for (i = 0; i < rdev->pm.dpm.num_ps; i++) { + kfree(rdev->pm.dpm.ps[i].ps_priv); + } + kfree(rdev->pm.dpm.ps); + kfree(rdev->pm.dpm.priv); +} + +u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low) +{ + struct trinity_ps *requested_state = trinity_get_ps(rdev->pm.dpm.requested_ps); + + if (low) + return requested_state->levels[0].sclk; + else + return requested_state->levels[requested_state->num_levels - 1].sclk; +} + +u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low) +{ + struct trinity_power_info *pi = trinity_get_pi(rdev); + + return pi->sys_info.bootup_uma_clk; +} diff --git a/drivers/gpu/drm/radeon/trinity_dpm.h b/drivers/gpu/drm/radeon/trinity_dpm.h new file mode 100644 index 0000000..15e050f --- /dev/null +++ b/drivers/gpu/drm/radeon/trinity_dpm.h @@ -0,0 +1,110 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __TRINITY_DPM_H__ +#define __TRINITY_DPM_H__ + +#include "sumo_dpm.h" + +#define TRINITY_SIZEOF_DPM_STATE_TABLE (SMU_SCLK_DPM_STATE_1_CNTL_0 - SMU_SCLK_DPM_STATE_0_CNTL_0) + +struct trinity_pl { + u32 sclk; + u8 vddc_index; + u8 ds_divider_index; + u8 ss_divider_index; + u8 allow_gnb_slow; + u8 force_nbp_state; + u8 display_wm; + u8 vce_wm; +}; + +#define TRINITY_POWERSTATE_FLAGS_NBPS_FORCEHIGH (1 << 0) +#define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOHIGH (1 << 1) +#define TRINITY_POWERSTATE_FLAGS_NBPS_LOCKTOLOW (1 << 2) + +#define TRINITY_POWERSTATE_FLAGS_BAPM_DISABLE (1 << 0) + +struct trinity_ps { + u32 num_levels; + struct trinity_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS]; + + u32 nbps_flags; + u32 bapm_flags; + + u8 Dpm0PgNbPsLo; + u8 Dpm0PgNbPsHi; + u8 DpmXNbPsLo; + u8 DpmXNbPsHi; +}; + +#define TRINITY_NUM_NBPSTATES 4 + +struct trinity_sys_info { + u32 bootup_uma_clk; + u32 bootup_sclk; + u32 min_sclk; + u32 nb_dpm_enable; + u32 nbp_mclk[TRINITY_NUM_NBPSTATES]; + u32 nbp_nclk[TRINITY_NUM_NBPSTATES]; + u16 nbp_voltage_index[TRINITY_NUM_NBPSTATES]; + u16 bootup_nb_voltage_index; + u8 htc_tmp_lmt; + u8 htc_hyst_lmt; + struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table; + struct sumo_vid_mapping_table vid_mapping_table; + u32 uma_channel_number; +}; + +struct trinity_power_info { + u32 at[SUMO_MAX_HARDWARE_POWERLEVELS]; + u32 dpm_interval; + u32 thermal_auto_throttling; + struct trinity_sys_info sys_info; + struct trinity_pl boot_pl; + struct trinity_ps current_ps; + u32 min_sclk_did; + bool enable_nbps_policy; + bool voltage_drop_in_dce; + bool override_dynamic_mgpg; + bool enable_gfx_clock_gating; + bool enable_gfx_power_gating; + bool enable_mg_clock_gating; + bool enable_gfx_dynamic_mgpg; + bool enable_auto_thermal_throttling; + bool enable_dpm; + bool enable_sclk_ds; +}; + +#define TRINITY_AT_DFLT 30 + +/* trinity_smc.c */ +int trinity_dpm_config(struct radeon_device *rdev, bool enable); +int trinity_dpm_force_state(struct radeon_device *rdev, u32 n); +int trinity_dpm_no_forced_level(struct radeon_device *rdev); +int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev, + bool enable); +int trinity_gfx_dynamic_mgpg_config(struct radeon_device *rdev); +void trinity_acquire_mutex(struct radeon_device *rdev); +void trinity_release_mutex(struct radeon_device *rdev); + +#endif diff --git a/drivers/gpu/drm/radeon/trinity_smc.c b/drivers/gpu/drm/radeon/trinity_smc.c new file mode 100644 index 0000000..60ffc1e --- /dev/null +++ b/drivers/gpu/drm/radeon/trinity_smc.c @@ -0,0 +1,110 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include "drmP.h" +#include "radeon.h" +#include "trinityd.h" +#include "trinity_dpm.h" +#include "ppsmc.h" + +struct trinity_ps *trinity_get_ps(struct radeon_ps *rps); +struct trinity_power_info *trinity_get_pi(struct radeon_device *rdev); + +static int trinity_notify_message_to_smu(struct radeon_device *rdev, u32 id) +{ + int i; + u32 v = 0; + + WREG32(SMC_MESSAGE_0, id); + for (i = 0; i < rdev->usec_timeout; i++) { + if (RREG32(SMC_RESP_0) != 0) + break; + udelay(1); + } + v = RREG32(SMC_RESP_0); + + if (v != 1) { + if (v == 0xFF) { + DRM_ERROR("SMC failed to handle the message!\n"); + return -EINVAL; + } else if (v == 0xFE) { + DRM_ERROR("Unknown SMC message!\n"); + return -EINVAL; + } + } + + return 0; +} + +int trinity_dpm_config(struct radeon_device *rdev, bool enable) +{ + if (enable) + WREG32_SMC(SMU_SCRATCH0, 1); + else + WREG32_SMC(SMU_SCRATCH0, 0); + + return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DPM_Config); +} + +int trinity_dpm_force_state(struct radeon_device *rdev, u32 n) +{ + WREG32_SMC(SMU_SCRATCH0, n); + + return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DPM_ForceState); +} + +int trinity_dpm_no_forced_level(struct radeon_device *rdev) +{ + return trinity_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel); +} + +int trinity_dce_enable_voltage_adjustment(struct radeon_device *rdev, + bool enable) +{ + if (enable) + return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DCE_AllowVoltageAdjustment); + else + return trinity_notify_message_to_smu(rdev, PPSMC_MSG_DCE_RemoveVoltageAdjustment); +} + +int trinity_gfx_dynamic_mgpg_config(struct radeon_device *rdev) +{ + return trinity_notify_message_to_smu(rdev, PPSMC_MSG_PG_SIMD_Config); +} + +void trinity_acquire_mutex(struct radeon_device *rdev) +{ + int i; + + WREG32(SMC_INT_REQ, 1); + for (i = 0; i < rdev->usec_timeout; i++) { + if ((RREG32(SMC_INT_REQ) & 0xffff) == 1) + break; + udelay(1); + } +} + +void trinity_release_mutex(struct radeon_device *rdev) +{ + WREG32(SMC_INT_REQ, 0); +} diff --git a/drivers/gpu/drm/radeon/trinityd.h b/drivers/gpu/drm/radeon/trinityd.h new file mode 100644 index 0000000..b234d36 --- /dev/null +++ b/drivers/gpu/drm/radeon/trinityd.h @@ -0,0 +1,223 @@ +/* + * Copyright 2012 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Alex Deucher + */ +#ifndef _TRINITYD_H_ +#define _TRINITYD_H_ + +/* pm registers */ + +/* cg */ +#define CG_CGTT_LOCAL_0 0x0 +#define CG_CGTT_LOCAL_1 0x1 + +/* smc */ +#define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000 +# define STATE_VALID(x) ((x) << 0) +# define STATE_VALID_MASK (0xff << 0) +# define STATE_VALID_SHIFT 0 +# define CLK_DIVIDER(x) ((x) << 8) +# define CLK_DIVIDER_MASK (0xff << 8) +# define CLK_DIVIDER_SHIFT 8 +# define VID(x) ((x) << 16) +# define VID_MASK (0xff << 16) +# define VID_SHIFT 16 +# define LVRT(x) ((x) << 24) +# define LVRT_MASK (0xff << 24) +# define LVRT_SHIFT 24 +#define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004 +# define DS_DIV(x) ((x) << 0) +# define DS_DIV_MASK (0xff << 0) +# define DS_DIV_SHIFT 0 +# define DS_SH_DIV(x) ((x) << 8) +# define DS_SH_DIV_MASK (0xff << 8) +# define DS_SH_DIV_SHIFT 8 +# define DISPLAY_WM(x) ((x) << 16) +# define DISPLAY_WM_MASK (0xff << 16) +# define DISPLAY_WM_SHIFT 16 +# define VCE_WM(x) ((x) << 24) +# define VCE_WM_MASK (0xff << 24) +# define VCE_WM_SHIFT 24 + +#define SMU_SCLK_DPM_STATE_0_CNTL_3 0x1f00c +# define GNB_SLOW(x) ((x) << 0) +# define GNB_SLOW_MASK (0xff << 0) +# define GNB_SLOW_SHIFT 0 +# define FORCE_NBPS1(x) ((x) << 8) +# define FORCE_NBPS1_MASK (0xff << 8) +# define FORCE_NBPS1_SHIFT 8 +#define SMU_SCLK_DPM_STATE_0_AT 0x1f010 +# define AT(x) ((x) << 0) +# define AT_MASK (0xff << 0) +# define AT_SHIFT 0 + +#define SMU_SCLK_DPM_STATE_0_PG_CNTL 0x1f014 +# define PD_SCLK_DIVIDER(x) ((x) << 16) +# define PD_SCLK_DIVIDER_MASK (0xff << 16) +# define PD_SCLK_DIVIDER_SHIFT 16 + +#define SMU_SCLK_DPM_STATE_1_CNTL_0 0x1f020 + +#define SMU_SCLK_DPM_CNTL 0x1f100 +# define SCLK_DPM_EN(x) ((x) << 0) +# define SCLK_DPM_EN_MASK (0xff << 0) +# define SCLK_DPM_EN_SHIFT 0 +# define SCLK_DPM_BOOT_STATE(x) ((x) << 16) +# define SCLK_DPM_BOOT_STATE_MASK (0xff << 16) +# define SCLK_DPM_BOOT_STATE_SHIFT 16 +# define VOLTAGE_CHG_EN(x) ((x) << 24) +# define VOLTAGE_CHG_EN_MASK (0xff << 24) +# define VOLTAGE_CHG_EN_SHIFT 24 + +#define SMU_SCLK_DPM_TT_CNTL 0x1f108 +# define SCLK_TT_EN(x) ((x) << 0) +# define SCLK_TT_EN_MASK (0xff << 0) +# define SCLK_TT_EN_SHIFT 0 +#define SMU_SCLK_DPM_TTT 0x1f10c +# define LT(x) ((x) << 0) +# define LT_MASK (0xffff << 0) +# define LT_SHIFT 0 +# define HT(x) ((x) << 16) +# define HT_MASK (0xffff << 16) +# define HT_SHIFT 16 + +#define SMU_S_PG_CNTL 0x1f118 +# define DS_PG_EN(x) ((x) << 16) +# define DS_PG_EN_MASK (0xff << 16) +# define DS_PG_EN_SHIFT 16 + +#define GFX_POWER_GATING_CNTL 0x1f38c +# define PDS_DIV(x) ((x) << 0) +# define PDS_DIV_MASK (0xff << 0) +# define PDS_DIV_SHIFT 0 +# define SSSD(x) ((x) << 8) +# define SSSD_MASK (0xff << 8) +# define SSSD_SHIFT 8 + +#define PM_CONFIG 0x1f428 +# define SVI_Mode (1 << 29) + +#define PM_I_CNTL_1 0x1f464 +# define SCLK_DPM(x) ((x) << 0) +# define SCLK_DPM_MASK (0xff << 0) +# define SCLK_DPM_SHIFT 0 +# define DS_PG_CNTL(x) ((x) << 16) +# define DS_PG_CNTL_MASK (0xff << 16) +# define DS_PG_CNTL_SHIFT 16 +#define PM_TP 0x1f468 + +#define NB_PSTATE_CONFIG 0x1f5f8 +# define Dpm0PgNbPsLo(x) ((x) << 0) +# define Dpm0PgNbPsLo_MASK (3 << 0) +# define Dpm0PgNbPsLo_SHIFT 0 +# define Dpm0PgNbPsHi(x) ((x) << 2) +# define Dpm0PgNbPsHi_MASK (3 << 2) +# define Dpm0PgNbPsHi_SHIFT 2 +# define DpmXNbPsLo(x) ((x) << 4) +# define DpmXNbPsLo_MASK (3 << 4) +# define DpmXNbPsLo_SHIFT 4 +# define DpmXNbPsHi(x) ((x) << 6) +# define DpmXNbPsHi_MASK (3 << 6) +# define DpmXNbPsHi_SHIFT 6 + +#define DC_CAC_VALUE 0x1f908 + +#define GPU_CAC_AVRG_CNTL 0x1f920 +# define WINDOW_SIZE(x) ((x) << 0) +# define WINDOW_SIZE_MASK (0xff << 0) +# define WINDOW_SIZE_SHIFT 0 + +#define CC_SMU_MISC_FUSES 0xe0001004 +# define MinSClkDid(x) ((x) << 2) +# define MinSClkDid_MASK (0x7f << 2) +# define MinSClkDid_SHIFT 2 + +#define CC_SMU_TST_EFUSE1_MISC 0xe000101c +# define RB_BACKEND_DISABLE(x) ((x) << 16) +# define RB_BACKEND_DISABLE_MASK (3 << 16) +# define RB_BACKEND_DISABLE_SHIFT 16 + +#define SMU_SCRATCH_A 0xe0003024 + +#define SMU_SCRATCH0 0xe0003040 + +/* mmio */ +#define SMC_INT_REQ 0x220 + +#define SMC_MESSAGE_0 0x22c +#define SMC_RESP_0 0x230 + +#define GENERAL_PWRMGT 0x670 +# define GLOBAL_PWRMGT_EN (1 << 0) + +#define SCLK_PWRMGT_CNTL 0x678 +# define DYN_PWR_DOWN_EN (1 << 2) +# define RESET_BUSY_CNT (1 << 4) +# define RESET_SCLK_CNT (1 << 5) +# define DYN_GFX_CLK_OFF_EN (1 << 7) +# define GFX_CLK_FORCE_ON (1 << 8) +# define DYNAMIC_PM_EN (1 << 21) + +#define TARGET_AND_CURRENT_PROFILE_INDEX 0x684 +# define TARGET_STATE(x) ((x) << 0) +# define TARGET_STATE_MASK (0xf << 0) +# define TARGET_STATE_SHIFT 0 +# define CURRENT_STATE(x) ((x) << 4) +# define CURRENT_STATE_MASK (0xf << 4) +# define CURRENT_STATE_SHIFT 4 + +#define CG_GIPOTS 0x6d8 +# define CG_GIPOT(x) ((x) << 16) +# define CG_GIPOT_MASK (0xffff << 16) +# define CG_GIPOT_SHIFT 16 + +#define CG_PG_CTRL 0x6e0 +# define SP(x) ((x) << 0) +# define SP_MASK (0xffff << 0) +# define SP_SHIFT 0 +# define SU(x) ((x) << 16) +# define SU_MASK (0xffff << 16) +# define SU_SHIFT 16 + +#define CG_THERMAL_INT_CTRL 0x738 +# define DIG_THERM_INTH(x) ((x) << 0) +# define DIG_THERM_INTH_MASK (0xff << 0) +# define DIG_THERM_INTH_SHIFT 0 +# define DIG_THERM_INTL(x) ((x) << 8) +# define DIG_THERM_INTL_MASK (0xff << 8) +# define DIG_THERM_INTL_SHIFT 8 +# define THERM_INTH_MASK (1 << 24) +# define THERM_INTL_MASK (1 << 25) + +#define CG_CG_VOLTAGE_CNTL 0x770 +# define EN (1 << 9) + +#define HW_REV 0x5564 +# define ATI_REV_ID_MASK (0xf << 28) +# define ATI_REV_ID_SHIFT 28 +/* 0 = A0, 1 = A1, 2 = B0, 3 = C0, etc. */ + +#define CGTS_SM_CTRL_REG 0x9150 + +#define GB_ADDR_CONFIG 0x98f8 + +#endif