+ Krzysztof
On 2015년 06월 22일 18:10, Inki Dae wrote:
On 2015년 06월 12일 21:59, Hyungwon Hwang wrote:
The clock which was named as 'pll_clk' is actually not the clock source of PLL in MIPI DSI. This patch fixes this disagreement.
Mr. Kukjin and Krzysztof, can you give me Acked-by or Singed-off-by? I'd like to merge this patch to mainline through drm-next.
Thanks, Inki Dae
Signed-off-by: Hyungwon Hwang human.hwang@samsung.com
Changes before:
Changes for v6:
- None
arch/arm/boot/dts/exynos4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index e20cdc2..1538d7a 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -167,7 +167,7 @@ phys = <&mipi_phy 1>; phy-names = "dsim"; clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
clock-names = "bus_clk", "pll_clk";
clock-names = "bus_clk", "sclk_mipi";-- 1.9.1
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