Currently the pixel formats that are supported by a plane object are hard-coded to three entries.
This is not correct since depending on the particular hardware block (DECON7, FIMD, VP, etc.) the supported formats are different.
Let each block specify its own list of formats.
Signed-off-by: Tobias Jakobi tjakobi@math.uni-bielefeld.de --- drivers/gpu/drm/exynos/exynos7_drm_decon.c | 7 +++++++ drivers/gpu/drm/exynos/exynos_drm_fimd.c | 7 +++++++ drivers/gpu/drm/exynos/exynos_drm_plane.c | 10 ++-------- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 7 +++++++ drivers/gpu/drm/exynos/exynos_mixer.c | 18 ++++++++++++++++++ 5 files changed, 41 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index ca70599..73788a1 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -42,6 +42,11 @@
#define WINDOWS_NR 2
+static const uint32_t decon_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, +}; + struct decon_context { struct device *dev; struct drm_device *drm_dev; @@ -767,6 +772,8 @@ static int decon_bind(struct device *dev, struct device *master, void *data) }
plane_config.possible_crtcs = 1 << ctx->pipe; + plane_config.pixel_formats = decon_formats; + plane_config.num_pixel_formats = ARRAY_SIZE(decon_formats);
for (i = 0; i < WINDOWS_NR; i++) { plane_config.type = (i == ctx->default_win) ? diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 93fbaa5..1db8db7 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -144,6 +144,11 @@ static struct fimd_driver_data exynos5_fimd_driver_data = { .has_vtsel = 1, };
+static const uint32_t fimd_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, +}; + struct fimd_context { struct device *dev; struct drm_device *drm_dev; @@ -1005,6 +1010,8 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) ctx->pipe = priv->pipe++;
plane_config.possible_crtcs = 1 << ctx->pipe; + plane_config.pixel_formats = fimd_formats; + plane_config.num_pixel_formats = ARRAY_SIZE(fimd_formats);
for (i = 0; i < WINDOWS_NR; i++) { plane_config.type = (i == ctx->default_win) ? diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index d24b32a..563d471 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -19,12 +19,6 @@ #include "exynos_drm_gem.h" #include "exynos_drm_plane.h"
-static const uint32_t formats[] = { - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_NV12, -}; - /* * This function is to get X or Y size shown via screen. This needs length and * start position of CRTC. @@ -212,8 +206,8 @@ int exynos_plane_init(struct drm_device *dev,
err = drm_universal_plane_init(dev, &exynos_plane->base, config->possible_crtcs, - &exynos_plane_funcs, formats, - ARRAY_SIZE(formats), config->type); + &exynos_plane_funcs, config->pixel_formats, + config->num_pixel_formats, config->type); if (err) { DRM_ERROR("failed to initialize plane\n"); return err; diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index ca7cc8a..94d2e84 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -33,6 +33,11 @@ #define ctx_from_connector(c) container_of(c, struct vidi_context, \ connector)
+static const uint32_t vidi_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, +}; + struct vidi_context { struct exynos_drm_display display; struct platform_device *pdev; @@ -470,6 +475,8 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) vidi_ctx_initialize(ctx, drm_dev);
plane_config.possible_crtcs = 1 << ctx->pipe; + plane_config.pixel_formats = vidi_formats; + plane_config.num_pixel_formats = ARRAY_SIZE(vidi_formats);
for (i = 0; i < WINDOWS_NR; i++) { plane_config.type = (i == ctx->default_win) ? diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 207d5c9..50df981 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -43,6 +43,7 @@
#define MIXER_WIN_NR 3 #define MIXER_DEFAULT_WIN 0 +#define MIXER_VP_WIN 2
#define MIXER_PIXELFORMAT_RGB565 4 #define MIXER_PIXELFORMAT_ARGB1555 5 @@ -123,6 +124,15 @@ static const u8 filter_cr_horiz_tap4[] = { 70, 59, 48, 37, 27, 19, 11, 5, };
+static const uint32_t mixer_formats[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, +}; + +static const uint32_t vp_formats[] = { + DRM_FORMAT_NV12, +}; + static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id) { return readl(res->vp_regs + reg_id); @@ -1240,6 +1250,14 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data) DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY; plane_config.zpos = i;
+ if (i == MIXER_VP_WIN && ctx->vp_enabled) { + plane_config.pixel_formats = vp_formats; + plane_config.num_pixel_formats = ARRAY_SIZE(vp_formats); + } else { + plane_config.pixel_formats = mixer_formats; + plane_config.num_pixel_formats = ARRAY_SIZE(mixer_formats); + } + ret = exynos_plane_init(drm_dev, &ctx->planes[i], &plane_config); if (ret) return ret;