Hi Sylwester,
This patch contains one typo.
On 10/30/20 9:51 PM, Sylwester Nawrocki wrote:
Add documentation for new optional properties in the exynos bus nodes: interconnects, #interconnect-cells, samsung,data-clock-ratio. These properties allow to specify the SoC interconnect structure which then allows the interconnect consumer devices to request specific bandwidth requirements.
Signed-off-by: Artur Świgoń a.swigon@samsung.com Signed-off-by: Sylwester Nawrocki s.nawrocki@samsung.com
Changes for v7:
- bus-width property replaced with samsung,data-clock-ratio,
- the interconnect consumer bindings used instead of vendor specific properties
Changes for v6:
- added dts example of bus hierarchy definition and the interconnect consumer,
- added new bus-width property.
Changes for v5:
- exynos,interconnect-parent-node renamed to samsung,interconnect-parent
.../devicetree/bindings/devfreq/exynos-bus.txt | 68 +++++++++++++++++++++- 1 file changed, 66 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index e71f752..e34175c 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -51,6 +51,16 @@ Optional properties only for parent bus device:
- exynos,saturation-ratio: the percentage value which is used to calibrate the performance count against total cycle count.
+Optional properties for interconnect functionality (QoS frequency constraints): +- #interconnect-cells: should be 0. +- interconnects: as documented in ../interconnect.txt, describes a path
- at the higher level interconnects used by this interconnect provider.
- If this interconnect provider is a parent of a top level interconnect
- provider the property contains only one phandle.
+- samsung,data-clock-ratio: ratio of the data troughput in B/s to minimum data
s/troughput/throughput
- clock frequency in Hz, default value is 8 when this property is missing.
Detailed correlation between sub-blocks and power line according to Exynos SoC:
- In case of Exynos3250, there are two power line as following: VDD_MIF |--- DMC
@@ -135,7 +145,7 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC: |--- PERIC (Fixed clock rate) |--- FSYS (Fixed clock rate)
-Example1: +Example 1: Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to power line (regulator). The MIF (Memory Interface) AXI bus is used to transfer data between DRAM and CPU and uses the VDD_MIF regulator. @@ -184,7 +194,7 @@ Example1: |L5 |200000 |200000 |400000 |300000 | ||1000000 |
-Example2 : +Example 2: The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi is listed below:
@@ -419,3 +429,57 @@ Example2 : devfreq = <&bus_leftbus>; status = "okay"; };
+Example 3:
- An interconnect path "bus_display -- bus_leftbus -- bus_dmc" on
- Exynos4412 SoC with video mixer as an interconnect consumer device.
- soc {
bus_dmc: bus_dmc {compatible = "samsung,exynos-bus";clocks = <&clock CLK_DIV_DMC>;clock-names = "bus";operating-points-v2 = <&bus_dmc_opp_table>;samsung,data-clock-ratio = <4>;#interconnect-cells = <0>;};bus_leftbus: bus_leftbus {compatible = "samsung,exynos-bus";clocks = <&clock CLK_DIV_GDL>;clock-names = "bus";operating-points-v2 = <&bus_leftbus_opp_table>;#interconnect-cells = <0>;interconnects = <&bus_dmc>;};bus_display: bus_display {compatible = "samsung,exynos-bus";clocks = <&clock CLK_ACLK160>;clock-names = "bus";operating-points-v2 = <&bus_display_opp_table>;#interconnect-cells = <0>;interconnects = <&bus_leftbus &bus_dmc>;
About adding two icc_node, I queried you on patch2.
};bus_dmc_opp_table: opp_table1 {compatible = "operating-points-v2";/* ... */}bus_leftbus_opp_table: opp_table3 {compatible = "operating-points-v2";/* ... */};bus_display_opp_table: opp_table4 {compatible = "operating-points-v2";/* .. */};&mixer {compatible = "samsung,exynos4212-mixer";interconnects = <&bus_display &bus_dmc>;/* ... */};- };