On Son, 2012-10-07 at 15:06 +0200, Christian König wrote:
Based on Dmitries work, but splitting the code into page directory and page table handling makes it far more readable and (hopefully) more reliable.
Allocations of page tables are made from the SA on demand, that should still work fine since all page tables are of the same size.
Also using the fact that allocations from the SA are mostly continuously (except for end of buffer wraps and under very high memory pressure) to group updates send to the chipset specific code into larger chunks.
v3: mostly a rewrite of Dmitries previous patch.
Signed-off-by: Dmitry Cherkasov Dmitrii.Cherkasov@amd.com Signed-off-by: Christian König deathsimple@vodafone.de
Tested-by: Michel Dänzer michel.daenzer@amd.com
There are some checkpatch errors and warnings though, e.g. trailing whitespace.
Also, I noticed a few typos:
- /* initial clear the page directory */
'Initially'
@@ -865,6 +906,155 @@ uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr) }
/**
- radeon_vm_update_pdes - make sure that page directory is valid
- @rdev: radeon_device pointer
- @vm: requested vm
- @start: start of GPU address range
- @end: end of GPU address range
- Allocates new page tables if nessasary
'necessary'