From: Abhinav Kumar abhinavk@codeaurora.org
Setting the DSI PLL src in probe doesn't provide the clock driver sufficient time to reclaim unused clock resources from coreboot resulting in warnings from clock driver.
Move the DSI PLL src setting to modeset_init() so that the clock driver can claim unused display clock resources before the display driver requests for them again.
Signed-off-by: Abhinav Kumar abhinavk@codeaurora.org --- drivers/gpu/drm/msm/dsi/dsi.c | 6 ++++ drivers/gpu/drm/msm/dsi/dsi.h | 1 + drivers/gpu/drm/msm/dsi/dsi_manager.c | 66 +++++++++++++++++++++++------------ 3 files changed, 51 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index 9fb612c17a39..ea100f15ce0d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -211,6 +211,12 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, priv = dev->dev_private; msm_dsi->dev = dev;
+ ret = msm_dsi_manager_pll_setup(msm_dsi); + if (ret) { + dev_err(dev->dev, "failed to setup pll: %d\n", ret); + goto fail; + } + ret = msm_dsi_host_modeset_init(msm_dsi->host, dev); if (ret) { dev_err(dev->dev, "failed to modeset init host: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 356953010256..a9fed9ab17b2 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -101,6 +101,7 @@ void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags); int msm_dsi_manager_register(struct msm_dsi *msm_dsi); void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi); bool msm_dsi_manager_validate_current_config(u8 id); +int msm_dsi_manager_pll_setup(struct msm_dsi *msm_dsi);
/* msm dsi */ static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi) diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 980b1bba8477..40da1229565e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -72,25 +72,60 @@ static int dsi_mgr_parse_dual_dsi(struct device_node *np, int id) return 0; }
-static int dsi_mgr_setup_components(int id) +static int msm_dsi_pll_configure(struct msm_dsi *msm_dsi, bool is_dual) { - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id); + struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(msm_dsi->id); struct msm_dsi *clk_master_dsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER); struct msm_dsi *clk_slave_dsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE); struct msm_dsi_pll *src_pll; - int ret; - - if (!IS_DUAL_DSI()) { - ret = msm_dsi_host_register(msm_dsi->host, true); - if (ret) - return ret; + int ret = 0;
+ if (!is_dual) { msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE); src_pll = msm_dsi_phy_get_pll(msm_dsi->phy); if (IS_ERR(src_pll)) return PTR_ERR(src_pll); ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll); + } else { + /* PLL0 is to drive both 2 DSI link clocks in Dual DSI mode. */ + msm_dsi_phy_set_usecase(clk_master_dsi->phy, + MSM_DSI_PHY_MASTER); + msm_dsi_phy_set_usecase(clk_slave_dsi->phy, + MSM_DSI_PHY_SLAVE); + src_pll = msm_dsi_phy_get_pll(clk_master_dsi->phy); + if (IS_ERR(src_pll)) + return PTR_ERR(src_pll); + ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll); + if (ret) + return ret; + ret = msm_dsi_host_set_src_pll(other_dsi->host, src_pll); + } + + return ret; +} + +int msm_dsi_manager_pll_setup(struct msm_dsi *msm_dsi) +{ + int ret; + + if (!IS_DUAL_DSI()) + ret = msm_dsi_pll_configure(msm_dsi, true); + else + ret = msm_dsi_pll_configure(msm_dsi, false); + + return ret; +} + +static int dsi_mgr_setup_components(int id) +{ + struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); + struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id); + int ret; + + if (!IS_DUAL_DSI()) { + ret = msm_dsi_host_register(msm_dsi->host, true); + if (ret) + return ret; } else if (!other_dsi) { ret = 0; } else { @@ -111,19 +146,6 @@ static int dsi_mgr_setup_components(int id) ret = msm_dsi_host_register(master_link_dsi->host, true); if (ret) return ret; - - /* PLL0 is to drive both 2 DSI link clocks in Dual DSI mode. */ - msm_dsi_phy_set_usecase(clk_master_dsi->phy, - MSM_DSI_PHY_MASTER); - msm_dsi_phy_set_usecase(clk_slave_dsi->phy, - MSM_DSI_PHY_SLAVE); - src_pll = msm_dsi_phy_get_pll(clk_master_dsi->phy); - if (IS_ERR(src_pll)) - return PTR_ERR(src_pll); - ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll); - if (ret) - return ret; - ret = msm_dsi_host_set_src_pll(other_dsi->host, src_pll); }
return ret;