As reported by TI spruh73x RM, the LCD pixel clock (LCD_PCLK) frequency is obtained by dividing LCD_CLK, the LCD controller reference clock, for CLKDIV:
LCD_PCLK = LCD_CLK / CLKDIV
where CLKDIV must be greater than 1.
Therefore LCD_CLK must be set to 'req_rate * CLKDIV' instead of req_rate and the real LCD_CLK rate must be compared with 'req_rate * CLKDIV' and not with req_rate. Passing req_rate instead of 'req_rate * CLKDIV' to the tilcdc_pclk_diff routine caused it to fail even if LCD_CLK was properly set.
Signed-off-by: Dario Binacchi dariobin@libero.it
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c index 30213708fc99..02f56c9a5da5 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c @@ -203,7 +203,7 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc) struct drm_device *dev = crtc->dev; struct tilcdc_drm_private *priv = dev->dev_private; struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc); - unsigned long clk_rate, real_rate, req_rate; + unsigned long clk_rate, real_rate, req_rate, clk_div_rate; unsigned int clkdiv; int ret;
@@ -211,10 +211,11 @@ static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
/* mode.clock is in KHz, set_rate wants parameter in Hz */ req_rate = crtc->mode.clock * 1000; - - ret = clk_set_rate(priv->clk, req_rate * clkdiv); + /* LCD clock divisor input rate */ + clk_div_rate = req_rate * clkdiv; + ret = clk_set_rate(priv->clk, clk_div_rate); clk_rate = clk_get_rate(priv->clk); - if (ret < 0 || tilcdc_pclk_diff(req_rate, clk_rate) > 5) { + if (ret < 0 || tilcdc_pclk_diff(clk_div_rate, clk_rate) > 5) { /* * If we fail to set the clock rate (some architectures don't * use the common clock framework yet and may not implement