This is a note to let you know that I've just added the patch titled
mtd: spi-nor: cadence-quadspi: add a delay in write sequence
to the 4.14-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summ...
The filename of the patch is: mtd-spi-nor-cadence-quadspi-add-a-delay-in-write-sequence.patch and it can be found in the queue-4.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let stable@vger.kernel.org know about it.
From foo@baz Mon 11 Nov 2019 10:07:22 AM CET
From: Mathieu Poirier mathieu.poirier@linaro.org Date: Thu, 5 Sep 2019 10:17:49 -0600 Subject: mtd: spi-nor: cadence-quadspi: add a delay in write sequence To: stable@vger.kernel.org Cc: linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-omap@vger.kernel.org, linux-i2c@vger.kernel.org, linux-pci@vger.kernel.org, linux-mtd@lists.infradead.org Message-ID: 20190905161759.28036-9-mathieu.poirier@linaro.org
From: Vignesh R vigneshr@ti.com
commit 61dc8493bae9ba82a1c72edbc6c6065f6a94456a upstream
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access Controller programming sequence, a delay equal to couple of QSPI master clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY to handle this and set this flag for TI 66AK2G SoC.
[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
Signed-off-by: Vignesh R vigneshr@ti.com Acked-by: Marek Vasut marek.vasut@gmail.com Signed-off-by: Cyrille Pitchen cyrille.pitchen@wedev4u.fr Signed-off-by: Mathieu Poirier mathieu.poirier@linaro.org Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org --- drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-)
--- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -38,6 +38,9 @@ #define CQSPI_NAME "cadence-qspi" #define CQSPI_MAX_CHIPSELECT 16
+/* Quirks */ +#define CQSPI_NEEDS_WR_DELAY BIT(0) + struct cqspi_st;
struct cqspi_flash_pdata { @@ -76,6 +79,7 @@ struct cqspi_st { u32 fifo_depth; u32 fifo_width; u32 trigger_address; + u32 wr_delay; struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; };
@@ -623,6 +627,15 @@ static int cqspi_indirect_write_execute( reinit_completion(&cqspi->transfer_complete); writel(CQSPI_REG_INDIRECTWR_START_MASK, reg_base + CQSPI_REG_INDIRECTWR); + /* + * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access + * Controller programming sequence, couple of cycles of + * QSPI_REF_CLK delay is required for the above bit to + * be internally synchronized by the QSPI module. Provide 5 + * cycles of delay. + */ + if (cqspi->wr_delay) + ndelay(cqspi->wr_delay);
while (remaining > 0) { size_t write_words, mod_bytes; @@ -1184,6 +1197,7 @@ static int cqspi_probe(struct platform_d struct cqspi_st *cqspi; struct resource *res; struct resource *res_ahb; + unsigned long data; int ret; int irq;
@@ -1241,6 +1255,10 @@ static int cqspi_probe(struct platform_d }
cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); + data = (unsigned long)of_device_get_match_data(dev); + if (data & CQSPI_NEEDS_WR_DELAY) + cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, + cqspi->master_ref_clk_hz);
ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0, pdev->name, cqspi); @@ -1312,7 +1330,14 @@ static const struct dev_pm_ops cqspi__de #endif
static const struct of_device_id cqspi_dt_ids[] = { - {.compatible = "cdns,qspi-nor",}, + { + .compatible = "cdns,qspi-nor", + .data = (void *)0, + }, + { + .compatible = "ti,k2g-qspi", + .data = (void *)CQSPI_NEEDS_WR_DELAY, + }, { /* end of table */ } };
Patches currently in stable-queue which might be from mathieu.poirier@linaro.org are
queue-4.14/mailbox-reset-txdone_method-txdone_by_poll-if-client-knows_txdone.patch queue-4.14/mtd-spi-nor-cadence-quadspi-add-a-delay-in-write-sequence.patch queue-4.14/misc-pci_endpoint_test-fix-bug_on-error-during-pci_disable_msi.patch queue-4.14/asoc-tlv320dac31xx-mark-expected-switch-fall-through.patch queue-4.14/pci-dra7xx-add-shutdown-handler-to-cleanly-turn-off-clocks.patch queue-4.14/asoc-tlv320aic31xx-handle-inverted-bclk-in-non-dsp-modes.patch queue-4.14/mtd-spi-nor-enable-4b-opcodes-for-mx66l51235l.patch queue-4.14/cpufreq-ti-cpufreq-add-missing-of_node_put.patch queue-4.14/asoc-davinci-kill-bug_on-usage.patch queue-4.14/mfd-palmas-assign-the-right-powerhold-mask-for-tps65917.patch queue-4.14/asoc-davinci-mcasp-fix-an-error-handling-path-in-davinci_mcasp_probe.patch queue-4.14/misc-pci_endpoint_test-prevent-some-integer-overflows.patch queue-4.14/asoc-davinci-mcasp-handle-return-value-of-devm_kasprintf.patch queue-4.14/i2c-omap-trigger-bus-recovery-in-lockup-case.patch queue-4.14/usb-dwc3-allow-disabling-of-metastability-workaround.patch