rk3399 platform have dfi controller can monitor ddr load, and dcf controller to handle ddr register so we can get the right ddr frequency and make ddr controller happy work(which will implement in bl31). So we do ddr frequency scaling with following flow:
kernel bl31
monitor ddr load | | get_target_rate | | pass rate to bl31 clk_set_rate(ddr) --------------------->run dcf flow | | | | wait dcf interrupt<-------------------trigger dcf interrupt | | return
Lin Huang (4): rockchip: rockchip: add new clock-type for the ddrclk clk: rockchip: rk3399: add ddrc clock support PM / devfreq: rockchip: add devfreq driver for rk3399 dmc drm/rockchip: Add dmc notifier in vop driver
drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-ddr.c | 147 ++++++++++ drivers/clk/rockchip/clk-rk3399.c | 16 + drivers/clk/rockchip/clk.c | 9 + drivers/clk/rockchip/clk.h | 27 ++ drivers/devfreq/Kconfig | 2 +- drivers/devfreq/Makefile | 1 + drivers/devfreq/rockchip/Kconfig | 14 + drivers/devfreq/rockchip/Makefile | 2 + drivers/devfreq/rockchip/rk3399_dmc.c | 438 ++++++++++++++++++++++++++++ drivers/devfreq/rockchip/rockchip_dmc.c | 132 +++++++++ drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 51 +++- include/dt-bindings/clock/rk3399-cru.h | 1 + include/soc/rockchip/rockchip_dmc.h | 44 +++ 14 files changed, 882 insertions(+), 3 deletions(-) create mode 100644 drivers/clk/rockchip/clk-ddr.c create mode 100644 drivers/devfreq/rockchip/Kconfig create mode 100644 drivers/devfreq/rockchip/Makefile create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c create mode 100644 drivers/devfreq/rockchip/rockchip_dmc.c create mode 100644 include/soc/rockchip/rockchip_dmc.h
On new rockchip platform(rk3399 etc), there have dcf controller to do ddr frequency scaling, and this controller will implement in arm-trust-firmware. We add a special clock-type to handle that.
Signed-off-by: Lin Huang hl@rock-chips.com --- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-ddr.c | 147 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.c | 9 +++ drivers/clk/rockchip/clk.h | 27 ++++++++ 4 files changed, 184 insertions(+) create mode 100644 drivers/clk/rockchip/clk-ddr.c
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index f47a2fa..b5f2c8e 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -8,6 +8,7 @@ obj-y += clk-pll.o obj-y += clk-cpu.o obj-y += clk-inverter.o obj-y += clk-mmc-phase.o +obj-y += clk-ddr.o obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
obj-y += clk-rk3036.o diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c new file mode 100644 index 0000000..5b6630d --- /dev/null +++ b/drivers/clk/rockchip/clk-ddr.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co. Ltd. + * Author: Lin Huang hl@rock-chips.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/of.h> +#include <linux/slab.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include "clk.h" + +struct rockchip_ddrclk { + struct clk_hw hw; + void __iomem *reg_base; + int mux_offset; + int mux_shift; + int mux_width; + int mux_flag; + int div_shift; + int div_width; + int div_flag; + spinlock_t *lock; +}; + +#define to_rockchip_ddrclk_hw(hw) container_of(hw, struct rockchip_ddrclk, hw) +#define val_mask(width) ((1 << (width)) - 1) + +static int rockchip_ddrclk_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw); + unsigned long flags; + + spin_lock_irqsave(ddrclk->lock, flags); + + /* TODO: set ddr rate in bl31 */ + + spin_unlock_irqrestore(ddrclk->lock, flags); + + return 0; +} + +static unsigned long +rockchip_ddrclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw); + int val; + + val = clk_readl(ddrclk->reg_base + + ddrclk->mux_offset) >> ddrclk->div_shift; + val &= val_mask(ddrclk->div_width); + + return DIV_ROUND_UP_ULL((u64)parent_rate, val + 1); +} + +static long clk_ddrclk_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + return rate; +} + +static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw) +{ + struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw); + int num_parents = clk_hw_get_num_parents(hw); + u32 val; + + val = clk_readl(ddrclk->reg_base + + ddrclk->mux_offset) >> ddrclk->mux_shift; + val &= val_mask(ddrclk->mux_width); + + if (val >= num_parents) + return -EINVAL; + + return val; +} + +static const struct clk_ops rockchip_ddrclk_ops = { + .recalc_rate = rockchip_ddrclk_recalc_rate, + .set_rate = rockchip_ddrclk_set_rate, + .round_rate = clk_ddrclk_round_rate, + .get_parent = rockchip_ddrclk_get_parent, +}; + +struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, + const char *const *parent_names, + u8 num_parents, int mux_offset, + int mux_shift, int mux_width, + int mux_flag, int div_shift, + int div_width, int div_flag, + void __iomem *reg_base, + spinlock_t *lock) +{ + struct rockchip_ddrclk *ddrclk; + struct clk_init_data init; + struct clk *clk; + int ret; + + ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL); + if (!ddrclk) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.parent_names = parent_names; + init.num_parents = num_parents; + init.ops = &rockchip_ddrclk_ops; + + init.flags = flags; + init.flags |= CLK_SET_RATE_NO_REPARENT; + init.flags |= CLK_GET_RATE_NOCACHE; + + ddrclk->reg_base = reg_base; + ddrclk->lock = lock; + ddrclk->hw.init = &init; + ddrclk->mux_offset = mux_offset; + ddrclk->mux_shift = mux_shift; + ddrclk->mux_width = mux_width; + ddrclk->mux_flag = mux_flag; + ddrclk->div_shift = div_shift; + ddrclk->div_width = div_width; + ddrclk->div_flag = div_flag; + + clk = clk_register(NULL, &ddrclk->hw); + if (IS_ERR(clk)) { + pr_err("%s: could not register ddrclk %s\n", __func__, name); + ret = PTR_ERR(clk); + goto free_ddrclk; + } + + return clk; + +free_ddrclk: + kfree(ddrclk); + return ERR_PTR(ret); +} diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index 7ffd134..6ac1aa5 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -484,6 +484,15 @@ void __init rockchip_clk_register_branches( list->gate_offset, list->gate_shift, list->gate_flags, flags, &ctx->lock); break; + case branch_ddrc: + clk = rockchip_clk_register_ddrclk( + list->name, list->flags, + list->parent_names, list->num_parents, + list->muxdiv_offset, list->mux_shift, + list->mux_width, list->mux_flags, + list->div_shift, list->div_width, + list->div_flags, ctx->reg_base, &ctx->lock); + break; }
/* none of the cases above matched */ diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 2194ffa..4033fe4 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -281,6 +281,13 @@ struct clk *rockchip_clk_register_mmc(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *reg, int shift);
+struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, + const char *const *parent_names, u8 num_parents, + int mux_offset, int mux_shift, int mux_width, + int mux_flag, int div_shift, int div_width, + int div_flag, void __iomem *reg_base, + spinlock_t *lock); + #define ROCKCHIP_INVERTER_HIWORD_MASK BIT(0)
struct clk *rockchip_clk_register_inverter(const char *name, @@ -299,6 +306,7 @@ enum rockchip_clk_branch_type { branch_mmc, branch_inverter, branch_factor, + branch_ddrc, };
struct rockchip_clk_branch { @@ -488,6 +496,25 @@ struct rockchip_clk_branch { .child = ch, \ }
+#define COMPOSITE_DDRC(_id, cname, pnames, f, mo, ms, mw, mf, \ + ds, dw, df) \ + { \ + .id = _id, \ + .branch_type = branch_ddrc, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .gate_offset = -1, \ + } + #define MUX(_id, cname, pnames, f, o, s, w, mf) \ { \ .id = _id, \
add ddrc clock setting, so we can do ddr frequency scaling on rk3399 platform in future.
Signed-off-by: Lin Huang hl@rock-chips.com --- drivers/clk/rockchip/clk-rk3399.c | 16 ++++++++++++++++ include/dt-bindings/clock/rk3399-cru.h | 1 + 2 files changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index f1d8e44..749ea59 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -118,6 +118,10 @@ PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" }; +PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", + "clk_ddrc_bpll_src", + "clk_ddrc_dpll_src", + "clk_ddrc_gpll_src" }; PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", @@ -1377,6 +1381,18 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, RK3368_CLKGATE_CON(13), 11, GFLAGS), + + /* ddrc */ + GATE(0, "clk_ddrc_lpll_src", "lpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(3), 0, GFLAGS), + GATE(0, "clk_ddrc_bpll_src", "bpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(3), 1, GFLAGS), + GATE(0, "clk_ddrc_dpll_src", "dpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(3), 2, GFLAGS), + GATE(0, "clk_ddrc_gpll_src", "gpll", CLK_IGNORE_UNUSED, + RK3399_CLKGATE_CON(3), 3, GFLAGS), + COMPOSITE_DDRC(SCLK_DDRCLK, "clk_ddrc", mux_ddrclk_p, CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(6), 4, 2, MFLAGS, 0, 3, DFLAGS), };
static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..8a0f0442 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,7 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_DDRCLK 168
#define DCLK_VOP0 180 #define DCLK_VOP1 181
Lin Huang,
On Wed, Jun 1, 2016 at 2:35 AM, Lin Huang hl@rock-chips.com wrote:
add ddrc clock setting, so we can do ddr frequency scaling on rk3399 platform in future.
Signed-off-by: Lin Huang hl@rock-chips.com
drivers/clk/rockchip/clk-rk3399.c | 16 ++++++++++++++++ include/dt-bindings/clock/rk3399-cru.h | 1 + 2 files changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index f1d8e44..749ea59 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -118,6 +118,10 @@ PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" }; +PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
"clk_ddrc_bpll_src","clk_ddrc_dpll_src","clk_ddrc_gpll_src" };PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", @@ -1377,6 +1381,18 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, RK3368_CLKGATE_CON(13), 11, GFLAGS),
/* ddrc */GATE(0, "clk_ddrc_lpll_src", "lpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 0, GFLAGS),GATE(0, "clk_ddrc_bpll_src", "bpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 1, GFLAGS),GATE(0, "clk_ddrc_dpll_src", "dpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 2, GFLAGS),GATE(0, "clk_ddrc_gpll_src", "gpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 3, GFLAGS),COMPOSITE_DDRC(SCLK_DDRCLK, "clk_ddrc", mux_ddrclk_p, CLK_IGNORE_UNUSED,RK3399_CLKSEL_CON(6), 4, 2, MFLAGS, 0, 3, DFLAGS),
It seems slightly unfortunate that we need CLK_IGNORE_UNUSED on these. Only one of these will ever be used at once and it would be awfully nice if the others could get gated, right?
...presumably this is needed because we might not have an actual driver for DDR Freq and we definitely want to make sure that clk_ddrc is enabled in that case. I guess what we really want is something like CLK_ENABLE_HAND_OFF eventually, but until then I think you might get slightly better behavior by getting rid of all of these CLK_IGNORE_UNUSED and setting "clk_ddrc" as a critical clock, either using the table in this file or the new flag.
};
static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..8a0f0442 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,7 @@ #define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167 +#define SCLK_DDRCLK 168
Almost certainly you'll want to create a separate patch for the dt-bindings change since it will need to land in a different tree so it can be pulled into both Heiko's clock topic branch and dts64 topic branch.
-Doug
Am Mittwoch, 1. Juni 2016, 08:24:48 schrieb Doug Anderson:
Lin Huang,
On Wed, Jun 1, 2016 at 2:35 AM, Lin Huang hl@rock-chips.com wrote:
add ddrc clock setting, so we can do ddr frequency scaling on rk3399 platform in future.
Signed-off-by: Lin Huang hl@rock-chips.com
drivers/clk/rockchip/clk-rk3399.c | 16 ++++++++++++++++ include/dt-bindings/clock/rk3399-cru.h | 1 + 2 files changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index f1d8e44..749ea59 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -118,6 +118,10 @@ PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",> "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" };
+PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
"clk_ddrc_bpll_src","clk_ddrc_dpll_src","clk_ddrc_gpll_src" };PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
"gpll_aclk_cci_src", "npll_aclk_cci_src",@@ -1377,6 +1381,18 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {> COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, RK3368_CLKGATE_CON(13), 11, GFLAGS),
/* ddrc */GATE(0, "clk_ddrc_lpll_src", "lpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 0, GFLAGS),GATE(0, "clk_ddrc_bpll_src", "bpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 1, GFLAGS),GATE(0, "clk_ddrc_dpll_src", "dpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 2, GFLAGS),GATE(0, "clk_ddrc_gpll_src", "gpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 3, GFLAGS),COMPOSITE_DDRC(SCLK_DDRCLK, "clk_ddrc", mux_ddrclk_p,CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(6), 4, 2, MFLAGS, 0, 3, DFLAGS),
It seems slightly unfortunate that we need CLK_IGNORE_UNUSED on these. Only one of these will ever be used at once and it would be awfully nice if the others could get gated, right?
...presumably this is needed because we might not have an actual driver for DDR Freq and we definitely want to make sure that clk_ddrc is enabled in that case. I guess what we really want is something like CLK_ENABLE_HAND_OFF eventually, but until then I think you might get slightly better behavior by getting rid of all of these CLK_IGNORE_UNUSED and setting "clk_ddrc" as a critical clock, either using the table in this file or the new flag.
My current feeling is that staying with the homegrown solution for critical clocks might be preferable until the clk-handoff mechanism lands as well, as our critical clocks fall into both categories and I'd like to not touch everything twice.
The clock above should be controlled by the dcf, so falls into the handoff category (critical until a driver picks up the clock).
Also mixing both new and old approach might get confusing.
But I'm definitly open to counter-arguments :-)
};
static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..8a0f0442 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,7 @@
#define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167
+#define SCLK_DDRCLK 168
Almost certainly you'll want to create a separate patch for the dt-bindings change since it will need to land in a different tree so it can be pulled into both Heiko's clock topic branch and dts64 topic branch.
correct.
Hi Doug&Heiko,
On 2016年06月01日 23:46, Heiko Stübner wrote:
Am Mittwoch, 1. Juni 2016, 08:24:48 schrieb Doug Anderson:
Lin Huang,
On Wed, Jun 1, 2016 at 2:35 AM, Lin Huang hl@rock-chips.com wrote:
add ddrc clock setting, so we can do ddr frequency scaling on rk3399 platform in future.
Signed-off-by: Lin Huang hl@rock-chips.com
drivers/clk/rockchip/clk-rk3399.c | 16 ++++++++++++++++ include/dt-bindings/clock/rk3399-cru.h | 1 + 2 files changed, 17 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index f1d8e44..749ea59 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -118,6 +118,10 @@ PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",> "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" };
+PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
"clk_ddrc_bpll_src","clk_ddrc_dpll_src","clk_ddrc_gpll_src" };PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
"gpll_aclk_cci_src", "npll_aclk_cci_src",@@ -1377,6 +1381,18 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {> COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, RK3368_CLKGATE_CON(13), 11, GFLAGS),
/* ddrc */GATE(0, "clk_ddrc_lpll_src", "lpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 0, GFLAGS),GATE(0, "clk_ddrc_bpll_src", "bpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 1, GFLAGS),GATE(0, "clk_ddrc_dpll_src", "dpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 2, GFLAGS),GATE(0, "clk_ddrc_gpll_src", "gpll", CLK_IGNORE_UNUSED,RK3399_CLKGATE_CON(3), 3, GFLAGS),COMPOSITE_DDRC(SCLK_DDRCLK, "clk_ddrc", mux_ddrclk_p,CLK_IGNORE_UNUSED, + RK3399_CLKSEL_CON(6), 4, 2, MFLAGS, 0, 3, DFLAGS),
It seems slightly unfortunate that we need CLK_IGNORE_UNUSED on these. Only one of these will ever be used at once and it would be awfully nice if the others could get gated, right?
...presumably this is needed because we might not have an actual driver for DDR Freq and we definitely want to make sure that clk_ddrc is enabled in that case. I guess what we really want is something like CLK_ENABLE_HAND_OFF eventually, but until then I think you might get slightly better behavior by getting rid of all of these CLK_IGNORE_UNUSED and setting "clk_ddrc" as a critical clock, either using the table in this file or the new flag.
My current feeling is that staying with the homegrown solution for critical clocks might be preferable until the clk-handoff mechanism lands as well, as our critical clocks fall into both categories and I'd like to not touch everything twice.
The clock above should be controlled by the dcf, so falls into the handoff category (critical until a driver picks up the clock).
Also mixing both new and old approach might get confusing.
But I'm definitly open to counter-arguments :-)
I will remove CLK_IGNORE_UNUSED flag and set "clk_ddrc" as critical clock in next version. Besides, i think we should also set "clk_ddrc_dpll_src" as critical clock, since we always use dpll as ddr clock source, and it should always on.
};
static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
diff --git a/include/dt-bindings/clock/rk3399-cru.h b/include/dt-bindings/clock/rk3399-cru.h index 50a44cf..8a0f0442 100644 --- a/include/dt-bindings/clock/rk3399-cru.h +++ b/include/dt-bindings/clock/rk3399-cru.h @@ -131,6 +131,7 @@
#define SCLK_DPHY_RX0_CFG 165 #define SCLK_RMII_SRC 166 #define SCLK_PCIEPHY_REF100M 167
+#define SCLK_DDRCLK 168
Almost certainly you'll want to create a separate patch for the dt-bindings change since it will need to land in a different tree so it can be pulled into both Heiko's clock topic branch and dts64 topic branch.
correct.
will fix next version, thanks.
Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
there is dfi controller on rk3399 platform, it can monitor ddr load, register this controller to devfreq framework, and default to use simple_ondeamnd policy, and do ddr frequency scaling base on this result.
Signed-off-by: Lin Huang hl@rock-chips.com --- drivers/devfreq/Kconfig | 2 +- drivers/devfreq/Makefile | 1 + drivers/devfreq/rockchip/Kconfig | 14 + drivers/devfreq/rockchip/Makefile | 2 + drivers/devfreq/rockchip/rk3399_dmc.c | 438 ++++++++++++++++++++++++++++++++ drivers/devfreq/rockchip/rockchip_dmc.c | 132 ++++++++++ include/soc/rockchip/rockchip_dmc.h | 44 ++++ 7 files changed, 632 insertions(+), 1 deletion(-) create mode 100644 drivers/devfreq/rockchip/Kconfig create mode 100644 drivers/devfreq/rockchip/Makefile create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c create mode 100644 drivers/devfreq/rockchip/rockchip_dmc.c create mode 100644 include/soc/rockchip/rockchip_dmc.h
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 78dac0e..a883744 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -101,5 +101,5 @@ config ARM_TEGRA_DEVFREQ operating frequencies and voltages with OPP support.
source "drivers/devfreq/event/Kconfig" - +source "drivers/devfreq/rockchip/Kconfig" endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 09f11d9..48e2ae6 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o # DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
# DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ diff --git a/drivers/devfreq/rockchip/Kconfig b/drivers/devfreq/rockchip/Kconfig new file mode 100644 index 0000000..617b5fe --- /dev/null +++ b/drivers/devfreq/rockchip/Kconfig @@ -0,0 +1,14 @@ +config ARM_ROCKCHIP_DMC_DEVFREQ + tristate "ARM ROCKCHIP DMC DEVFREQ Driver" + depends on ARCH_ROCKCHIP + help + This adds the DEVFREQ driver framework for the rockchip dmc. + +config ARM_RK3399_DMC_DEVFREQ + tristate "ARM RK3399 DMC DEVFREQ Driver" + depends on ARM_ROCKCHIP_DMC_DEVFREQ + select PM_OPP + select DEVFREQ_GOV_SIMPLE_ONDEMAND + help + This adds the DEVFREQ driver for the RK3399 dmc. It sets the frequency + for the memory controller and reads the usage counts from hardware. diff --git a/drivers/devfreq/rockchip/Makefile b/drivers/devfreq/rockchip/Makefile new file mode 100644 index 0000000..caca525 --- /dev/null +++ b/drivers/devfreq/rockchip/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ) += rockchip_dmc.o +obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o diff --git a/drivers/devfreq/rockchip/rk3399_dmc.c b/drivers/devfreq/rockchip/rk3399_dmc.c new file mode 100644 index 0000000..4907d38 --- /dev/null +++ b/drivers/devfreq/rockchip/rk3399_dmc.c @@ -0,0 +1,438 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * Author: Lin Huang hl@rock-chips.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/clk.h> +#include <linux/completion.h> +#include <linux/delay.h> +#include <linux/devfreq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/pm_opp.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/rwsem.h> +#include <linux/suspend.h> +#include <linux/syscore_ops.h> + +#include <soc/rockchip/rockchip_dmc.h> + +#define RK3399_DMC_NUM_CH 2 + +/* DDRMON_CTRL */ +#define DDRMON_CTRL 0x04 +#define CLR_DDRMON_CTRL (0x1f0000 << 0) +#define LPDDR4_EN (0x10001 << 4) +#define HARDWARE_EN (0x10001 << 3) +#define LPDDR3_EN (0x10001 << 2) +#define SOFTWARE_EN (0x10001 << 1) +#define TIME_CNT_EN (0x10001 << 0) + +#define DDRMON_CH0_COUNT_NUM 0x28 +#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c +#define DDRMON_CH1_COUNT_NUM 0x3c +#define DDRMON_CH1_DFI_ACCESS_NUM 0x40 + +/* pmu grf */ +#define PMUGRF_OS_REG2 0x308 +#define DDRTYPE_SHIFT 13 +#define DDRTYPE_MASK 7 + +enum { + DDR3 = 3, + LPDDR3 = 6, + LPDDR4 = 7, + UNUSED = 0xFF +}; + +struct dmc_usage { + u32 access; + u32 total; +}; + +struct rk3399_dmcfreq { + struct device *dev; + struct devfreq *devfreq; + struct devfreq_simple_ondemand_data ondemand_data; + struct clk *dmc_clk; + struct completion dcf_hold_completion; + struct dmc_usage ch_usage[RK3399_DMC_NUM_CH]; + struct mutex lock; + struct notifier_block dmc_nb; + int irq; + void __iomem *regs; + struct regmap *regmap_pmu; + struct regulator *vdd_center; + unsigned long rate, target_rate; + unsigned long volt, target_volt; +}; + +static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev); + struct dev_pm_opp *opp; + unsigned long old_clk_rate = dmcfreq->rate; + unsigned long target_volt, target_rate; + int err; + + rcu_read_lock(); + opp = devfreq_recommended_opp(dev, freq, flags); + if (IS_ERR(opp)) { + rcu_read_unlock(); + return PTR_ERR(opp); + } + target_rate = dev_pm_opp_get_freq(opp); + target_volt = dev_pm_opp_get_voltage(opp); + + opp = devfreq_recommended_opp(dev, &dmcfreq->rate, flags); + if (IS_ERR(opp)) { + rcu_read_unlock(); + return PTR_ERR(opp); + } + dmcfreq->volt = dev_pm_opp_get_voltage(opp); + rcu_read_unlock(); + + if (dmcfreq->rate == target_rate) + return 0; + + mutex_lock(&dmcfreq->lock); + + /* + * if frequency scaling from low to high, adjust voltage first; + * if frequency scaling from high to low, adjuset frequency first; + */ + if (old_clk_rate < target_rate) { + err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, + target_volt); + if (err) { + dev_err(dev, "Unable to set vol %lu\n", target_volt); + goto out; + } + } + + dmc_event(DMCFREQ_ADJUST); + err = clk_set_rate(dmcfreq->dmc_clk, target_rate); + if (err) { + dev_err(dev, + "Unable to set freq %lu. Current freq %lu. Error %d\n", + target_rate, old_clk_rate, err); + regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, + dmcfreq->volt); + dmc_event(DMCFREQ_FINISH); + goto out; + } + + /* wait until bcf irq happen, it means ddr scaling finish in bl31 */ + reinit_completion(&dmcfreq->dcf_hold_completion); + wait_for_completion(&dmcfreq->dcf_hold_completion); + dmc_event(DMCFREQ_FINISH); + + if (old_clk_rate > target_rate) + err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, + target_volt); + if (err) + dev_err(dev, "Unable to set vol %lu\n", target_volt); + + /* check the rate we get whether correct */ + dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk); + if (dmcfreq->rate != target_rate) { + dev_err(dev, "get wrong ddr frequency, Request freq %lu,\ + Current freq %lu\n", target_rate, dmcfreq->rate); + regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, + dmcfreq->volt); + } +out: + mutex_unlock(&dmcfreq->lock); + return err; +} + +static void rk3399_dmc_start_hardware_counter(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev); + void __iomem *dfi_regs = dmcfreq->regs; + u32 val; + u32 ddr_type; + + /* get ddr type */ + regmap_read(dmcfreq->regmap_pmu, PMUGRF_OS_REG2, &val); + ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK; + + /* clear DDRMON_CTRL setting */ + writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); + + /* set ddr type to dfi */ + if (ddr_type == LPDDR3) + writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); + else if (ddr_type == LPDDR4) + writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); + + /* enable count, use software mode */ + writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL); +} + +static void rk3399_dmc_stop_hardware_counter(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev); + void __iomem *dfi_regs = dmcfreq->regs; + u32 val; + + val = readl_relaxed(dfi_regs + DDRMON_CTRL); + val &= ~SOFTWARE_EN; + writel_relaxed(val, dfi_regs + DDRMON_CTRL); +} + +static int rk3399_dmc_get_busier_ch(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev); + u32 tmp, max = 0; + u32 i, busier_ch = 0; + void __iomem *dfi_regs = dmcfreq->regs; + + rk3399_dmc_stop_hardware_counter(dev); + + /* Find out which channel is busier */ + for (i = 0; i < RK3399_DMC_NUM_CH; i++) { + dmcfreq->ch_usage[i].access = readl_relaxed(dfi_regs + + DDRMON_CH0_DFI_ACCESS_NUM + i * 20); + dmcfreq->ch_usage[i].total = readl_relaxed(dfi_regs + + DDRMON_CH0_COUNT_NUM + i * 20); + tmp = dmcfreq->ch_usage[i].access; + if (tmp > max) { + busier_ch = i; + max = tmp; + } + } + rk3399_dmc_start_hardware_counter(dev); + + return busier_ch; +} + +static int rk3399_dmcfreq_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev); + int busier_ch; + + busier_ch = rk3399_dmc_get_busier_ch(dev); + stat->current_frequency = dmcfreq->rate; + stat->busy_time = dmcfreq->ch_usage[busier_ch].access; + stat->total_time = dmcfreq->ch_usage[busier_ch].total; + + return 0; +} + +static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev); + + *freq = dmcfreq->rate; + + return 0; +} + +static void rk3399_dmcfreq_exit(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev); + + devfreq_unregister_opp_notifier(dev, dmcfreq->devfreq); +} + +static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = { + .polling_ms = 200, + .target = rk3399_dmcfreq_target, + .get_dev_status = rk3399_dmcfreq_get_dev_status, + .get_cur_freq = rk3399_dmcfreq_get_cur_freq, + .exit = rk3399_dmcfreq_exit, +}; + +static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev) +{ + rockchip_dmc_disable(); + return 0; +} + +static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev) +{ + rockchip_dmc_enable(); + return 0; +} + +static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend, + rk3399_dmcfreq_resume); + +static int rk3399_dmc_enable_notify(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct rk3399_dmcfreq *dmcfreq = + container_of(nb, struct rk3399_dmcfreq, dmc_nb); + unsigned long freq = ULONG_MAX; + + if (event == DMC_ENABLE) { + devfreq_resume_device(dmcfreq->devfreq); + rk3399_dmc_start_hardware_counter(dmcfreq->dev); + return NOTIFY_OK; + } else if (event == DMC_DISABLE) { + devfreq_suspend_device(dmcfreq->devfreq); + rk3399_dmc_stop_hardware_counter(dmcfreq->dev); + + /* when disable dmc, set sdram to max frequency */ + rk3399_dmcfreq_target(dmcfreq->dev, &freq, 0); + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id) +{ + struct rk3399_dmcfreq *dmcfreq = dev_id; + + complete(&dmcfreq->dcf_hold_completion); + + return IRQ_HANDLED; +} + +static int rk3399_dmcfreq_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rk3399_dmcfreq *data; + struct resource *res; + int ret, irq; + struct device_node *np = pdev->dev.of_node, *node; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(&pdev->dev, "no dmc irq resource\n"); + return -EINVAL; + } + + data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL); + if (!data) + return -ENOMEM; + + mutex_init(&data->lock); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + data->regs = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->regs)) + return PTR_ERR(data->regs); + + data->vdd_center = devm_regulator_get(dev, "center"); + if (IS_ERR(data->vdd_center)) { + dev_err(dev, "Cannot get the regulator "center"\n"); + return PTR_ERR(data->vdd_center); + } + + data->dmc_clk = devm_clk_get(dev, "dmc_clk"); + if (IS_ERR(data->dmc_clk)) { + dev_err(dev, "Cannot get the clk dmc_clk\n"); + return PTR_ERR(data->dmc_clk); + }; + + /* + * We add a devfreq driver to our parent since it has a device tree node + * with operating points. + */ + if (dev_pm_opp_of_add_table(dev)) { + dev_err(dev, "Invalid operating-points in device tree.\n"); + return -EINVAL; + } + + of_property_read_u32(np, "upthreshold", + &data->ondemand_data.upthreshold); + + of_property_read_u32(np, "downdifferential", + &data->ondemand_data.downdifferential); + + data->devfreq = devfreq_add_device(dev, + &rk3399_devfreq_dmc_profile, + "simple_ondemand", + &data->ondemand_data); + if (IS_ERR(data->devfreq)) + return PTR_ERR(data->devfreq); + + devfreq_register_opp_notifier(dev, data->devfreq); + + data->dmc_nb.notifier_call = rk3399_dmc_enable_notify; + dmc_register_notifier(&data->dmc_nb); + + data->irq = irq; + ret = devm_request_irq(dev, irq, rk3399_dmc_irq, IRQF_ONESHOT, + dev_name(dev), data); + if (ret) { + dev_err(dev, "failed to request dmc irq: %d\n", ret); + return ret; + } + + init_completion(&data->dcf_hold_completion); + + /* try to find the optional reference to the pmu syscon */ + node = of_parse_phandle(np, "rockchip,pmu", 0); + if (node) { + data->regmap_pmu = syscon_node_to_regmap(node); + if (IS_ERR(data->regmap_pmu)) + return PTR_ERR(data->regmap_pmu); + } + data->dev = dev; + platform_set_drvdata(pdev, data); + + return 0; +} + +static int rk3399_dmcfreq_remove(struct platform_device *pdev) +{ + struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev); + + devfreq_remove_device(dmcfreq->devfreq); + regulator_put(dmcfreq->vdd_center); + + return 0; +} + +static const struct of_device_id rk3399dmc_devfreq_of_match[] = { + { .compatible = "rockchip,rk3399-dmc" }, + { }, +}; + +static struct platform_driver rk3399_dmcfreq_driver = { + .probe = rk3399_dmcfreq_probe, + .remove = rk3399_dmcfreq_remove, + .driver = { + .name = "rk3399-dmc-freq", + .pm = &rk3399_dmcfreq_pm, + .of_match_table = rk3399dmc_devfreq_of_match, + }, +}; +module_platform_driver(rk3399_dmcfreq_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework"); diff --git a/drivers/devfreq/rockchip/rockchip_dmc.c b/drivers/devfreq/rockchip/rockchip_dmc.c new file mode 100644 index 0000000..ecc6598 --- /dev/null +++ b/drivers/devfreq/rockchip/rockchip_dmc.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * Author: Lin Huang hl@rock-chips.com + * Base on: https://chromium-review.googlesource.com/#/c/231477/ + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include <linux/mutex.h> +#include <soc/rockchip/rockchip_dmc.h> + +static int num_wait; +static int num_disable; +static BLOCKING_NOTIFIER_HEAD(dmc_notifier_list); +static DEFINE_MUTEX(dmc_en_lock); +static DEFINE_MUTEX(dmc_sync_lock); + +void dmc_event(int event) +{ + mutex_lock(&dmc_sync_lock); + blocking_notifier_call_chain(&dmc_notifier_list, event, NULL); + mutex_unlock(&dmc_sync_lock); +} +EXPORT_SYMBOL_GPL(dmc_event); + +/** + * rockchip_dmc_enabled - Returns true if dmc freq is enabled, false otherwise. + */ +bool rockchip_dmc_enabled(void) +{ + return num_disable <= 0 && num_wait <= 1; +} +EXPORT_SYMBOL_GPL(rockchip_dmc_enabled); + +/** + * rockchip_dmc_enable - Enable dmc frequency scaling. Will only enable + * frequency scaling if there are 1 or fewer notifiers. Call to undo + * rockchip_dmc_disable. + */ +void rockchip_dmc_enable(void) +{ + mutex_lock(&dmc_en_lock); + num_disable--; + WARN_ON(num_disable < 0); + if (rockchip_dmc_enabled()) + dmc_event(DMC_ENABLE); + mutex_unlock(&dmc_en_lock); +} +EXPORT_SYMBOL_GPL(rockchip_dmc_enable); + +/** + * rockchip_dmc_disable - Disable dmc frequency scaling. Call when something + * cannot coincide with dmc frequency scaling. + */ +void rockchip_dmc_disable(void) +{ + mutex_lock(&dmc_en_lock); + if (rockchip_dmc_enabled()) + dmc_event(DMC_DISABLE); + num_disable++; + mutex_unlock(&dmc_en_lock); +} +EXPORT_SYMBOL_GPL(rockchip_dmc_disable); + +int dmc_register_notifier(struct notifier_block *nb) +{ + int ret; + + if (!nb) + return -EINVAL; + + ret = blocking_notifier_chain_register(&dmc_notifier_list, nb); + + return ret; +} +EXPORT_SYMBOL_GPL(dmc_register_notifier); + +int dmc_unregister_notifier(struct notifier_block *nb) +{ + int ret; + + if (!nb) + return -EINVAL; + + ret = blocking_notifier_chain_unregister(&dmc_notifier_list, nb); + + return ret; +} +EXPORT_SYMBOL_GPL(dmc_unregister_notifier); + +int rockchip_dmc_get(struct notifier_block *nb) +{ + if (!nb) + return -EINVAL; + + mutex_lock(&dmc_en_lock); + + /* if use two vop, need to disable dmc */ + if (num_wait == 1 && num_disable <= 0) + dmc_event(DMC_DISABLE); + num_wait++; + dmc_register_notifier(nb); + mutex_unlock(&dmc_en_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(rockchip_dmc_get); + +int rockchip_dmc_put(struct notifier_block *nb) +{ + if (!nb) + return -EINVAL; + + mutex_lock(&dmc_en_lock); + num_wait--; + + /* from 2 vop back to 1 vop, need enable dmc */ + if (num_wait == 1 && num_disable <= 0) + dmc_event(DMC_ENABLE); + dmc_unregister_notifier(nb); + mutex_unlock(&dmc_en_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(rockchip_dmc_put); diff --git a/include/soc/rockchip/rockchip_dmc.h b/include/soc/rockchip/rockchip_dmc.h new file mode 100644 index 0000000..6bb58d6 --- /dev/null +++ b/include/soc/rockchip/rockchip_dmc.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SOC_ROCKCHIP_DMC_H +#define __SOC_ROCKCHIP_DMC_H + +#include <linux/notifier.h> + +#define DMC_ENABLE 0 +#define DMC_DISABLE 1 +#define DMCFREQ_ADJUST 2 +#define DMCFREQ_FINISH 3 + +#ifdef CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ +int rockchip_dmc_get(struct notifier_block *nb); +int rockchip_dmc_put(struct notifier_block *nb); +#else +static inline int rockchip_dmc_get(struct notifier_block *nb) +{ + return 0; +} +static inline int rockchip_dmc_put(struct notifier_block *nb) +{ + return 0; +} +#endif + +void dmc_event(int event); +int dmc_register_notifier(struct notifier_block *nb); +int dmc_unregister_notifier(struct notifier_block *nb); +void rockchip_dmc_enable(void); +void rockchip_dmc_disable(void); +bool rockchip_dmc_enabled(void); +#endif
On Wed, Jun 1, 2016 at 6:35 PM, Lin Huang hl@rock-chips.com wrote:
there is dfi controller on rk3399 platform, it can monitor ddr load, register this controller to devfreq framework, and default to use simple_ondeamnd policy, and do ddr frequency scaling base on this result.
Signed-off-by: Lin Huang hl@rock-chips.com
drivers/devfreq/Kconfig | 2 +- drivers/devfreq/Makefile | 1 + drivers/devfreq/rockchip/Kconfig | 14 + drivers/devfreq/rockchip/Makefile | 2 + drivers/devfreq/rockchip/rk3399_dmc.c | 438 ++++++++++++++++++++++++++++++++ drivers/devfreq/rockchip/rockchip_dmc.c | 132 ++++++++++ include/soc/rockchip/rockchip_dmc.h | 44 ++++ 7 files changed, 632 insertions(+), 1 deletion(-) create mode 100644 drivers/devfreq/rockchip/Kconfig create mode 100644 drivers/devfreq/rockchip/Makefile create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c create mode 100644 drivers/devfreq/rockchip/rockchip_dmc.c create mode 100644 include/soc/rockchip/rockchip_dmc.h
/* check the rate we get whether correct */dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);if (dmcfreq->rate != target_rate) {dev_err(dev, "get wrong ddr frequency, Request freq %lu,\Current freq %lu\n", target_rate, dmcfreq->rate);regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,dmcfreq->volt);
Why do you need to check this and more importantly, why do you assume that dmvfreq->volt will be safe in this case? (what if the new dmcfreq->rate is larger than the old dmcfreq->rate after clk_get_rate?) Note that you didn't update dmcfreq->volt after clk_get_rate()
+EXPORT_SYMBOL_GPL(dmc_event); +EXPORT_SYMBOL_GPL(rockchip_dmc_enabled); +EXPORT_SYMBOL_GPL(rockchip_dmc_enable); +EXPORT_SYMBOL_GPL(rockchip_dmc_disable); +EXPORT_SYMBOL_GPL(dmc_register_notifier); +EXPORT_SYMBOL_GPL(dmc_unregister_notifier); +EXPORT_SYMBOL_GPL(rockchip_dmc_get); +EXPORT_SYMBOL_GPL(rockchip_dmc_put);
Do you really need to export all these device driver specific functions? Looks like a design flaw here.
Cheers, MyungJoo
Hi Myungloo Ham,
On 2016年06月01日 18:47, MyungJoo Ham wrote:
On Wed, Jun 1, 2016 at 6:35 PM, Lin Huang hl@rock-chips.com wrote:
there is dfi controller on rk3399 platform, it can monitor ddr load, register this controller to devfreq framework, and default to use simple_ondeamnd policy, and do ddr frequency scaling base on this result.
Signed-off-by: Lin Huang hl@rock-chips.com
drivers/devfreq/Kconfig | 2 +- drivers/devfreq/Makefile | 1 + drivers/devfreq/rockchip/Kconfig | 14 + drivers/devfreq/rockchip/Makefile | 2 + drivers/devfreq/rockchip/rk3399_dmc.c | 438 ++++++++++++++++++++++++++++++++ drivers/devfreq/rockchip/rockchip_dmc.c | 132 ++++++++++ include/soc/rockchip/rockchip_dmc.h | 44 ++++ 7 files changed, 632 insertions(+), 1 deletion(-) create mode 100644 drivers/devfreq/rockchip/Kconfig create mode 100644 drivers/devfreq/rockchip/Makefile create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c create mode 100644 drivers/devfreq/rockchip/rockchip_dmc.c create mode 100644 include/soc/rockchip/rockchip_dmc.h
/* check the rate we get whether correct */dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);if (dmcfreq->rate != target_rate) {dev_err(dev, "get wrong ddr frequency, Request freq %lu,\Current freq %lu\n", target_rate, dmcfreq->rate);regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,dmcfreq->volt);Why do you need to check this and more importantly, why do you assume that dmvfreq->volt will be safe in this case? (what if the new dmcfreq->rate is larger than the old dmcfreq->rate after clk_get_rate?) Note that you didn't update dmcfreq->volt after clk_get_rate()
Now we will set the ddr clock rate in bl31 use dcf controller(as i show in the patch cover letter), and there only two result we can get, set clock rate fail(ddr clock still in old rate) or set clock rate sucessful(use the new ddr rate), if the set rate fail, we should keep the voltage old value. Ah, you remind me, i should check clock rate before: if (old_clk_rate > target_rate) otherwise there have chance set high rate fail and use low voltage.
And about the dmcfreq->volt, i will update this value when into the function, throuth
opp = devfreq_recommended_opp(dev, &dmcfreq->rate, flags); if (IS_ERR(opp)) { rcu_read_unlock(); return PTR_ERR(opp); } dmcfreq->volt = dev_pm_opp_get_voltage(opp);
+EXPORT_SYMBOL_GPL(dmc_event); +EXPORT_SYMBOL_GPL(rockchip_dmc_enabled); +EXPORT_SYMBOL_GPL(rockchip_dmc_enable); +EXPORT_SYMBOL_GPL(rockchip_dmc_disable); +EXPORT_SYMBOL_GPL(dmc_register_notifier); +EXPORT_SYMBOL_GPL(dmc_unregister_notifier); +EXPORT_SYMBOL_GPL(rockchip_dmc_get); +EXPORT_SYMBOL_GPL(rockchip_dmc_put);
Do you really need to export all these device driver specific functions? Looks like a design flaw here.
there is some situation we need to disable ddr frequency scaling(connect two panel etc) on rk3399 platform, and it should be also needed on other rockchip platform, so i move these funticon as separate file.
Cheers, MyungJoo
Hi Lin,
This patch include the two features as following: - Monitor the ddr load - Control the ddr's clock with ondemand governor based on load
The "Monitor the ddr load" has the specific the address in SoC. Namely, it is separate the module. So, I implemented the devfreq-event framework[1] which was merged.
It is right method to separate two feature from your device driver. You can refer to patch[2][3]. The patch[2] show how to implement the "monitor the ddr load" by using Devfreq-Event framework and the patch[3] include the method how to implement the rk3399 dmc driver.
[1] Devfreq-Event framework - https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=f...
[2] Exynos Noc probe driver by using Devfreq-Event framework - https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=0...
[3] Exynos Busfreq driver using the devfreq-evnet framework to get the monitored data - https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=0...
If you have more information and help, please let me know. I'll help you.
Thanks, Chanwoo Choi
On Wed, Jun 1, 2016 at 6:35 PM, Lin Huang hl@rock-chips.com wrote:
there is dfi controller on rk3399 platform, it can monitor ddr load, register this controller to devfreq framework, and default to use simple_ondeamnd policy, and do ddr frequency scaling base on this result.
Signed-off-by: Lin Huang hl@rock-chips.com
drivers/devfreq/Kconfig | 2 +- drivers/devfreq/Makefile | 1 + drivers/devfreq/rockchip/Kconfig | 14 + drivers/devfreq/rockchip/Makefile | 2 + drivers/devfreq/rockchip/rk3399_dmc.c | 438 ++++++++++++++++++++++++++++++++ drivers/devfreq/rockchip/rockchip_dmc.c | 132 ++++++++++ include/soc/rockchip/rockchip_dmc.h | 44 ++++ 7 files changed, 632 insertions(+), 1 deletion(-) create mode 100644 drivers/devfreq/rockchip/Kconfig create mode 100644 drivers/devfreq/rockchip/Makefile create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c create mode 100644 drivers/devfreq/rockchip/rockchip_dmc.c create mode 100644 include/soc/rockchip/rockchip_dmc.h
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 78dac0e..a883744 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -101,5 +101,5 @@ config ARM_TEGRA_DEVFREQ operating frequencies and voltages with OPP support.
source "drivers/devfreq/event/Kconfig"
+source "drivers/devfreq/rockchip/Kconfig" endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 09f11d9..48e2ae6 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o # DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
# DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ diff --git a/drivers/devfreq/rockchip/Kconfig b/drivers/devfreq/rockchip/Kconfig new file mode 100644 index 0000000..617b5fe --- /dev/null +++ b/drivers/devfreq/rockchip/Kconfig @@ -0,0 +1,14 @@ +config ARM_ROCKCHIP_DMC_DEVFREQ
tristate "ARM ROCKCHIP DMC DEVFREQ Driver"depends on ARCH_ROCKCHIPhelpThis adds the DEVFREQ driver framework for the rockchip dmc.+config ARM_RK3399_DMC_DEVFREQ
tristate "ARM RK3399 DMC DEVFREQ Driver"depends on ARM_ROCKCHIP_DMC_DEVFREQselect PM_OPPselect DEVFREQ_GOV_SIMPLE_ONDEMANDhelpThis adds the DEVFREQ driver for the RK3399 dmc. It sets the frequencyfor the memory controller and reads the usage counts from hardware.diff --git a/drivers/devfreq/rockchip/Makefile b/drivers/devfreq/rockchip/Makefile new file mode 100644 index 0000000..caca525 --- /dev/null +++ b/drivers/devfreq/rockchip/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ) += rockchip_dmc.o +obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o diff --git a/drivers/devfreq/rockchip/rk3399_dmc.c b/drivers/devfreq/rockchip/rk3399_dmc.c new file mode 100644 index 0000000..4907d38 --- /dev/null +++ b/drivers/devfreq/rockchip/rk3399_dmc.c @@ -0,0 +1,438 @@ +/*
- Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- Author: Lin Huang hl@rock-chips.com
- This program is free software; you can redistribute it and/or modify it
- under the terms and conditions of the GNU General Public License,
- version 2, as published by the Free Software Foundation.
- This program is distributed in the hope it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
- */
+#include <linux/clk.h> +#include <linux/completion.h> +#include <linux/delay.h> +#include <linux/devfreq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/pm_opp.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/rwsem.h> +#include <linux/suspend.h> +#include <linux/syscore_ops.h>
+#include <soc/rockchip/rockchip_dmc.h>
+#define RK3399_DMC_NUM_CH 2
+/* DDRMON_CTRL */ +#define DDRMON_CTRL 0x04 +#define CLR_DDRMON_CTRL (0x1f0000 << 0) +#define LPDDR4_EN (0x10001 << 4) +#define HARDWARE_EN (0x10001 << 3) +#define LPDDR3_EN (0x10001 << 2) +#define SOFTWARE_EN (0x10001 << 1) +#define TIME_CNT_EN (0x10001 << 0)
+#define DDRMON_CH0_COUNT_NUM 0x28 +#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c +#define DDRMON_CH1_COUNT_NUM 0x3c +#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+/* pmu grf */ +#define PMUGRF_OS_REG2 0x308 +#define DDRTYPE_SHIFT 13 +#define DDRTYPE_MASK 7
+enum {
DDR3 = 3,LPDDR3 = 6,LPDDR4 = 7,UNUSED = 0xFF+};
+struct dmc_usage {
u32 access;u32 total;+};
+struct rk3399_dmcfreq {
struct device *dev;struct devfreq *devfreq;struct devfreq_simple_ondemand_data ondemand_data;struct clk *dmc_clk;struct completion dcf_hold_completion;struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];struct mutex lock;struct notifier_block dmc_nb;int irq;void __iomem *regs;struct regmap *regmap_pmu;struct regulator *vdd_center;unsigned long rate, target_rate;unsigned long volt, target_volt;+};
+static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
u32 flags)+{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);struct dev_pm_opp *opp;unsigned long old_clk_rate = dmcfreq->rate;unsigned long target_volt, target_rate;int err;rcu_read_lock();opp = devfreq_recommended_opp(dev, freq, flags);if (IS_ERR(opp)) {rcu_read_unlock();return PTR_ERR(opp);}target_rate = dev_pm_opp_get_freq(opp);target_volt = dev_pm_opp_get_voltage(opp);opp = devfreq_recommended_opp(dev, &dmcfreq->rate, flags);if (IS_ERR(opp)) {rcu_read_unlock();return PTR_ERR(opp);}dmcfreq->volt = dev_pm_opp_get_voltage(opp);rcu_read_unlock();if (dmcfreq->rate == target_rate)return 0;mutex_lock(&dmcfreq->lock);/** if frequency scaling from low to high, adjust voltage first;* if frequency scaling from high to low, adjuset frequency first;*/if (old_clk_rate < target_rate) {err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,target_volt);if (err) {dev_err(dev, "Unable to set vol %lu\n", target_volt);goto out;}}dmc_event(DMCFREQ_ADJUST);err = clk_set_rate(dmcfreq->dmc_clk, target_rate);if (err) {dev_err(dev,"Unable to set freq %lu. Current freq %lu. Error %d\n",target_rate, old_clk_rate, err);regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,dmcfreq->volt);dmc_event(DMCFREQ_FINISH);goto out;}/* wait until bcf irq happen, it means ddr scaling finish in bl31 */reinit_completion(&dmcfreq->dcf_hold_completion);wait_for_completion(&dmcfreq->dcf_hold_completion);dmc_event(DMCFREQ_FINISH);if (old_clk_rate > target_rate)err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,target_volt);if (err)dev_err(dev, "Unable to set vol %lu\n", target_volt);/* check the rate we get whether correct */dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);if (dmcfreq->rate != target_rate) {dev_err(dev, "get wrong ddr frequency, Request freq %lu,\Current freq %lu\n", target_rate, dmcfreq->rate);regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,dmcfreq->volt);}+out:
mutex_unlock(&dmcfreq->lock);return err;+}
+static void rk3399_dmc_start_hardware_counter(struct device *dev) +{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);void __iomem *dfi_regs = dmcfreq->regs;u32 val;u32 ddr_type;/* get ddr type */regmap_read(dmcfreq->regmap_pmu, PMUGRF_OS_REG2, &val);ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;/* clear DDRMON_CTRL setting */writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);/* set ddr type to dfi */if (ddr_type == LPDDR3)writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);else if (ddr_type == LPDDR4)writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);/* enable count, use software mode */writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);+}
+static void rk3399_dmc_stop_hardware_counter(struct device *dev) +{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);void __iomem *dfi_regs = dmcfreq->regs;u32 val;val = readl_relaxed(dfi_regs + DDRMON_CTRL);val &= ~SOFTWARE_EN;writel_relaxed(val, dfi_regs + DDRMON_CTRL);+}
+static int rk3399_dmc_get_busier_ch(struct device *dev) +{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);u32 tmp, max = 0;u32 i, busier_ch = 0;void __iomem *dfi_regs = dmcfreq->regs;rk3399_dmc_stop_hardware_counter(dev);/* Find out which channel is busier */for (i = 0; i < RK3399_DMC_NUM_CH; i++) {dmcfreq->ch_usage[i].access = readl_relaxed(dfi_regs +DDRMON_CH0_DFI_ACCESS_NUM + i * 20);dmcfreq->ch_usage[i].total = readl_relaxed(dfi_regs +DDRMON_CH0_COUNT_NUM + i * 20);tmp = dmcfreq->ch_usage[i].access;if (tmp > max) {busier_ch = i;max = tmp;}}rk3399_dmc_start_hardware_counter(dev);return busier_ch;+}
+static int rk3399_dmcfreq_get_dev_status(struct device *dev,
struct devfreq_dev_status *stat)+{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);int busier_ch;busier_ch = rk3399_dmc_get_busier_ch(dev);stat->current_frequency = dmcfreq->rate;stat->busy_time = dmcfreq->ch_usage[busier_ch].access;stat->total_time = dmcfreq->ch_usage[busier_ch].total;return 0;+}
+static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq) +{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);*freq = dmcfreq->rate;return 0;+}
+static void rk3399_dmcfreq_exit(struct device *dev) +{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);devfreq_unregister_opp_notifier(dev, dmcfreq->devfreq);+}
+static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
.polling_ms = 200,.target = rk3399_dmcfreq_target,.get_dev_status = rk3399_dmcfreq_get_dev_status,.get_cur_freq = rk3399_dmcfreq_get_cur_freq,.exit = rk3399_dmcfreq_exit,+};
+static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev) +{
rockchip_dmc_disable();return 0;+}
+static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev) +{
rockchip_dmc_enable();return 0;+}
+static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
rk3399_dmcfreq_resume);+static int rk3399_dmc_enable_notify(struct notifier_block *nb,
unsigned long event, void *data)+{
struct rk3399_dmcfreq *dmcfreq =container_of(nb, struct rk3399_dmcfreq, dmc_nb);unsigned long freq = ULONG_MAX;if (event == DMC_ENABLE) {devfreq_resume_device(dmcfreq->devfreq);rk3399_dmc_start_hardware_counter(dmcfreq->dev);return NOTIFY_OK;} else if (event == DMC_DISABLE) {devfreq_suspend_device(dmcfreq->devfreq);rk3399_dmc_stop_hardware_counter(dmcfreq->dev);/* when disable dmc, set sdram to max frequency */rk3399_dmcfreq_target(dmcfreq->dev, &freq, 0);return NOTIFY_OK;}return NOTIFY_DONE;+}
+static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id) +{
struct rk3399_dmcfreq *dmcfreq = dev_id;complete(&dmcfreq->dcf_hold_completion);return IRQ_HANDLED;+}
+static int rk3399_dmcfreq_probe(struct platform_device *pdev) +{
struct device *dev = &pdev->dev;struct rk3399_dmcfreq *data;struct resource *res;int ret, irq;struct device_node *np = pdev->dev.of_node, *node;irq = platform_get_irq(pdev, 0);if (irq < 0) {dev_err(&pdev->dev, "no dmc irq resource\n");return -EINVAL;}data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);if (!data)return -ENOMEM;mutex_init(&data->lock);res = platform_get_resource(pdev, IORESOURCE_MEM, 0);data->regs = devm_ioremap_resource(&pdev->dev, res);if (IS_ERR(data->regs))return PTR_ERR(data->regs);data->vdd_center = devm_regulator_get(dev, "center");if (IS_ERR(data->vdd_center)) {dev_err(dev, "Cannot get the regulator \"center\"\n");return PTR_ERR(data->vdd_center);}data->dmc_clk = devm_clk_get(dev, "dmc_clk");if (IS_ERR(data->dmc_clk)) {dev_err(dev, "Cannot get the clk dmc_clk\n");return PTR_ERR(data->dmc_clk);};/** We add a devfreq driver to our parent since it has a device tree node* with operating points.*/if (dev_pm_opp_of_add_table(dev)) {dev_err(dev, "Invalid operating-points in device tree.\n");return -EINVAL;}of_property_read_u32(np, "upthreshold",&data->ondemand_data.upthreshold);of_property_read_u32(np, "downdifferential",&data->ondemand_data.downdifferential);data->devfreq = devfreq_add_device(dev,&rk3399_devfreq_dmc_profile,"simple_ondemand",&data->ondemand_data);if (IS_ERR(data->devfreq))return PTR_ERR(data->devfreq);devfreq_register_opp_notifier(dev, data->devfreq);data->dmc_nb.notifier_call = rk3399_dmc_enable_notify;dmc_register_notifier(&data->dmc_nb);data->irq = irq;ret = devm_request_irq(dev, irq, rk3399_dmc_irq, IRQF_ONESHOT,dev_name(dev), data);if (ret) {dev_err(dev, "failed to request dmc irq: %d\n", ret);return ret;}init_completion(&data->dcf_hold_completion);/* try to find the optional reference to the pmu syscon */node = of_parse_phandle(np, "rockchip,pmu", 0);if (node) {data->regmap_pmu = syscon_node_to_regmap(node);if (IS_ERR(data->regmap_pmu))return PTR_ERR(data->regmap_pmu);}data->dev = dev;platform_set_drvdata(pdev, data);return 0;+}
+static int rk3399_dmcfreq_remove(struct platform_device *pdev) +{
struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);devfreq_remove_device(dmcfreq->devfreq);regulator_put(dmcfreq->vdd_center);return 0;+}
+static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
{ .compatible = "rockchip,rk3399-dmc" },{ },+};
+static struct platform_driver rk3399_dmcfreq_driver = {
.probe = rk3399_dmcfreq_probe,.remove = rk3399_dmcfreq_remove,.driver = {.name = "rk3399-dmc-freq",.pm = &rk3399_dmcfreq_pm,.of_match_table = rk3399dmc_devfreq_of_match,},+}; +module_platform_driver(rk3399_dmcfreq_driver);
+MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework"); diff --git a/drivers/devfreq/rockchip/rockchip_dmc.c b/drivers/devfreq/rockchip/rockchip_dmc.c new file mode 100644 index 0000000..ecc6598 --- /dev/null +++ b/drivers/devfreq/rockchip/rockchip_dmc.c @@ -0,0 +1,132 @@ +/*
- Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- Author: Lin Huang hl@rock-chips.com
- This program is free software; you can redistribute it and/or modify it
- under the terms and conditions of the GNU General Public License,
- version 2, as published by the Free Software Foundation.
- This program is distributed in the hope it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
- */
+#include <linux/mutex.h> +#include <soc/rockchip/rockchip_dmc.h>
+static int num_wait; +static int num_disable; +static BLOCKING_NOTIFIER_HEAD(dmc_notifier_list); +static DEFINE_MUTEX(dmc_en_lock); +static DEFINE_MUTEX(dmc_sync_lock);
+void dmc_event(int event) +{
mutex_lock(&dmc_sync_lock);blocking_notifier_call_chain(&dmc_notifier_list, event, NULL);mutex_unlock(&dmc_sync_lock);+} +EXPORT_SYMBOL_GPL(dmc_event);
+/**
- rockchip_dmc_enabled - Returns true if dmc freq is enabled, false otherwise.
- */
+bool rockchip_dmc_enabled(void) +{
return num_disable <= 0 && num_wait <= 1;+} +EXPORT_SYMBOL_GPL(rockchip_dmc_enabled);
+/**
- rockchip_dmc_enable - Enable dmc frequency scaling. Will only enable
- frequency scaling if there are 1 or fewer notifiers. Call to undo
- rockchip_dmc_disable.
- */
+void rockchip_dmc_enable(void) +{
mutex_lock(&dmc_en_lock);num_disable--;WARN_ON(num_disable < 0);if (rockchip_dmc_enabled())dmc_event(DMC_ENABLE);mutex_unlock(&dmc_en_lock);+} +EXPORT_SYMBOL_GPL(rockchip_dmc_enable);
+/**
- rockchip_dmc_disable - Disable dmc frequency scaling. Call when something
- cannot coincide with dmc frequency scaling.
- */
+void rockchip_dmc_disable(void) +{
mutex_lock(&dmc_en_lock);if (rockchip_dmc_enabled())dmc_event(DMC_DISABLE);num_disable++;mutex_unlock(&dmc_en_lock);+} +EXPORT_SYMBOL_GPL(rockchip_dmc_disable);
+int dmc_register_notifier(struct notifier_block *nb) +{
int ret;if (!nb)return -EINVAL;ret = blocking_notifier_chain_register(&dmc_notifier_list, nb);return ret;+} +EXPORT_SYMBOL_GPL(dmc_register_notifier);
+int dmc_unregister_notifier(struct notifier_block *nb) +{
int ret;if (!nb)return -EINVAL;ret = blocking_notifier_chain_unregister(&dmc_notifier_list, nb);return ret;+} +EXPORT_SYMBOL_GPL(dmc_unregister_notifier);
+int rockchip_dmc_get(struct notifier_block *nb) +{
if (!nb)return -EINVAL;mutex_lock(&dmc_en_lock);/* if use two vop, need to disable dmc */if (num_wait == 1 && num_disable <= 0)dmc_event(DMC_DISABLE);num_wait++;dmc_register_notifier(nb);mutex_unlock(&dmc_en_lock);return 0;+} +EXPORT_SYMBOL_GPL(rockchip_dmc_get);
+int rockchip_dmc_put(struct notifier_block *nb) +{
if (!nb)return -EINVAL;mutex_lock(&dmc_en_lock);num_wait--;/* from 2 vop back to 1 vop, need enable dmc */if (num_wait == 1 && num_disable <= 0)dmc_event(DMC_ENABLE);dmc_unregister_notifier(nb);mutex_unlock(&dmc_en_lock);return 0;+} +EXPORT_SYMBOL_GPL(rockchip_dmc_put); diff --git a/include/soc/rockchip/rockchip_dmc.h b/include/soc/rockchip/rockchip_dmc.h new file mode 100644 index 0000000..6bb58d6 --- /dev/null +++ b/include/soc/rockchip/rockchip_dmc.h @@ -0,0 +1,44 @@ +/*
- Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- This program is free software; you can redistribute it and/or modify it
- under the terms and conditions of the GNU General Public License,
- version 2, as published by the Free Software Foundation.
- This program is distributed in the hope it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
- */
+#ifndef __SOC_ROCKCHIP_DMC_H +#define __SOC_ROCKCHIP_DMC_H
+#include <linux/notifier.h>
+#define DMC_ENABLE 0 +#define DMC_DISABLE 1 +#define DMCFREQ_ADJUST 2 +#define DMCFREQ_FINISH 3
+#ifdef CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ +int rockchip_dmc_get(struct notifier_block *nb); +int rockchip_dmc_put(struct notifier_block *nb); +#else +static inline int rockchip_dmc_get(struct notifier_block *nb) +{
return 0;+} +static inline int rockchip_dmc_put(struct notifier_block *nb) +{
return 0;+} +#endif
+void dmc_event(int event); +int dmc_register_notifier(struct notifier_block *nb); +int dmc_unregister_notifier(struct notifier_block *nb); +void rockchip_dmc_enable(void); +void rockchip_dmc_disable(void); +bool rockchip_dmc_enabled(void);
+#endif
1.9.1
Hi Chanwoo Choi,
I just check the devfreq-event framework code, it is good, i will do more dig to see whether it can fit for rk3399 dmc, thank you.
On 2016年06月01日 19:47, Chanwoo Choi wrote:
Hi Lin,
This patch include the two features as following:
- Monitor the ddr load
- Control the ddr's clock with ondemand governor based on load
The "Monitor the ddr load" has the specific the address in SoC. Namely, it is separate the module. So, I implemented the devfreq-event framework[1] which was merged.
It is right method to separate two feature from your device driver. You can refer to patch[2][3]. The patch[2] show how to implement the "monitor the ddr load" by using Devfreq-Event framework and the patch[3] include the method how to implement the rk3399 dmc driver.
[1] Devfreq-Event framework
[2] Exynos Noc probe driver by using Devfreq-Event framework
[3] Exynos Busfreq driver using the devfreq-evnet framework to get the monitored data
If you have more information and help, please let me know. I'll help you.
Thanks, Chanwoo Choi
On Wed, Jun 1, 2016 at 6:35 PM, Lin Huang hl@rock-chips.com wrote:
there is dfi controller on rk3399 platform, it can monitor ddr load, register this controller to devfreq framework, and default to use simple_ondeamnd policy, and do ddr frequency scaling base on this result.
Signed-off-by: Lin Huang hl@rock-chips.com
drivers/devfreq/Kconfig | 2 +- drivers/devfreq/Makefile | 1 + drivers/devfreq/rockchip/Kconfig | 14 + drivers/devfreq/rockchip/Makefile | 2 + drivers/devfreq/rockchip/rk3399_dmc.c | 438 ++++++++++++++++++++++++++++++++ drivers/devfreq/rockchip/rockchip_dmc.c | 132 ++++++++++ include/soc/rockchip/rockchip_dmc.h | 44 ++++ 7 files changed, 632 insertions(+), 1 deletion(-) create mode 100644 drivers/devfreq/rockchip/Kconfig create mode 100644 drivers/devfreq/rockchip/Makefile create mode 100644 drivers/devfreq/rockchip/rk3399_dmc.c create mode 100644 drivers/devfreq/rockchip/rockchip_dmc.c create mode 100644 include/soc/rockchip/rockchip_dmc.h
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 78dac0e..a883744 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -101,5 +101,5 @@ config ARM_TEGRA_DEVFREQ operating frequencies and voltages with OPP support.
source "drivers/devfreq/event/Kconfig"
+source "drivers/devfreq/rockchip/Kconfig" endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 09f11d9..48e2ae6 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o # DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
# DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ diff --git a/drivers/devfreq/rockchip/Kconfig b/drivers/devfreq/rockchip/Kconfig new file mode 100644 index 0000000..617b5fe --- /dev/null +++ b/drivers/devfreq/rockchip/Kconfig @@ -0,0 +1,14 @@ +config ARM_ROCKCHIP_DMC_DEVFREQ
tristate "ARM ROCKCHIP DMC DEVFREQ Driver"depends on ARCH_ROCKCHIPhelpThis adds the DEVFREQ driver framework for the rockchip dmc.+config ARM_RK3399_DMC_DEVFREQ
tristate "ARM RK3399 DMC DEVFREQ Driver"depends on ARM_ROCKCHIP_DMC_DEVFREQselect PM_OPPselect DEVFREQ_GOV_SIMPLE_ONDEMANDhelpThis adds the DEVFREQ driver for the RK3399 dmc. It sets the frequencyfor the memory controller and reads the usage counts from hardware.diff --git a/drivers/devfreq/rockchip/Makefile b/drivers/devfreq/rockchip/Makefile new file mode 100644 index 0000000..caca525 --- /dev/null +++ b/drivers/devfreq/rockchip/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ) += rockchip_dmc.o +obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o diff --git a/drivers/devfreq/rockchip/rk3399_dmc.c b/drivers/devfreq/rockchip/rk3399_dmc.c new file mode 100644 index 0000000..4907d38 --- /dev/null +++ b/drivers/devfreq/rockchip/rk3399_dmc.c @@ -0,0 +1,438 @@ +/*
- Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- Author: Lin Huang hl@rock-chips.com
- This program is free software; you can redistribute it and/or modify it
- under the terms and conditions of the GNU General Public License,
- version 2, as published by the Free Software Foundation.
- This program is distributed in the hope it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
- */
+#include <linux/clk.h> +#include <linux/completion.h> +#include <linux/delay.h> +#include <linux/devfreq.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/pm_opp.h> +#include <linux/regmap.h> +#include <linux/regulator/consumer.h> +#include <linux/rwsem.h> +#include <linux/suspend.h> +#include <linux/syscore_ops.h>
+#include <soc/rockchip/rockchip_dmc.h>
+#define RK3399_DMC_NUM_CH 2
+/* DDRMON_CTRL */ +#define DDRMON_CTRL 0x04 +#define CLR_DDRMON_CTRL (0x1f0000 << 0) +#define LPDDR4_EN (0x10001 << 4) +#define HARDWARE_EN (0x10001 << 3) +#define LPDDR3_EN (0x10001 << 2) +#define SOFTWARE_EN (0x10001 << 1) +#define TIME_CNT_EN (0x10001 << 0)
+#define DDRMON_CH0_COUNT_NUM 0x28 +#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c +#define DDRMON_CH1_COUNT_NUM 0x3c +#define DDRMON_CH1_DFI_ACCESS_NUM 0x40
+/* pmu grf */ +#define PMUGRF_OS_REG2 0x308 +#define DDRTYPE_SHIFT 13 +#define DDRTYPE_MASK 7
+enum {
DDR3 = 3,LPDDR3 = 6,LPDDR4 = 7,UNUSED = 0xFF+};
+struct dmc_usage {
u32 access;u32 total;+};
+struct rk3399_dmcfreq {
struct device *dev;struct devfreq *devfreq;struct devfreq_simple_ondemand_data ondemand_data;struct clk *dmc_clk;struct completion dcf_hold_completion;struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];struct mutex lock;struct notifier_block dmc_nb;int irq;void __iomem *regs;struct regmap *regmap_pmu;struct regulator *vdd_center;unsigned long rate, target_rate;unsigned long volt, target_volt;+};
+static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
u32 flags)+{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);struct dev_pm_opp *opp;unsigned long old_clk_rate = dmcfreq->rate;unsigned long target_volt, target_rate;int err;rcu_read_lock();opp = devfreq_recommended_opp(dev, freq, flags);if (IS_ERR(opp)) {rcu_read_unlock();return PTR_ERR(opp);}target_rate = dev_pm_opp_get_freq(opp);target_volt = dev_pm_opp_get_voltage(opp);opp = devfreq_recommended_opp(dev, &dmcfreq->rate, flags);if (IS_ERR(opp)) {rcu_read_unlock();return PTR_ERR(opp);}dmcfreq->volt = dev_pm_opp_get_voltage(opp);rcu_read_unlock();if (dmcfreq->rate == target_rate)return 0;mutex_lock(&dmcfreq->lock);/** if frequency scaling from low to high, adjust voltage first;* if frequency scaling from high to low, adjuset frequency first;*/if (old_clk_rate < target_rate) {err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,target_volt);if (err) {dev_err(dev, "Unable to set vol %lu\n", target_volt);goto out;}}dmc_event(DMCFREQ_ADJUST);err = clk_set_rate(dmcfreq->dmc_clk, target_rate);if (err) {dev_err(dev,"Unable to set freq %lu. Current freq %lu. Error %d\n",target_rate, old_clk_rate, err);regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,dmcfreq->volt);dmc_event(DMCFREQ_FINISH);goto out;}/* wait until bcf irq happen, it means ddr scaling finish in bl31 */reinit_completion(&dmcfreq->dcf_hold_completion);wait_for_completion(&dmcfreq->dcf_hold_completion);dmc_event(DMCFREQ_FINISH);if (old_clk_rate > target_rate)err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,target_volt);if (err)dev_err(dev, "Unable to set vol %lu\n", target_volt);/* check the rate we get whether correct */dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);if (dmcfreq->rate != target_rate) {dev_err(dev, "get wrong ddr frequency, Request freq %lu,\Current freq %lu\n", target_rate, dmcfreq->rate);regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,dmcfreq->volt);}+out:
mutex_unlock(&dmcfreq->lock);return err;+}
+static void rk3399_dmc_start_hardware_counter(struct device *dev) +{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);void __iomem *dfi_regs = dmcfreq->regs;u32 val;u32 ddr_type;/* get ddr type */regmap_read(dmcfreq->regmap_pmu, PMUGRF_OS_REG2, &val);ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;/* clear DDRMON_CTRL setting */writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);/* set ddr type to dfi */if (ddr_type == LPDDR3)writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);else if (ddr_type == LPDDR4)writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);/* enable count, use software mode */writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);+}
+static void rk3399_dmc_stop_hardware_counter(struct device *dev) +{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);void __iomem *dfi_regs = dmcfreq->regs;u32 val;val = readl_relaxed(dfi_regs + DDRMON_CTRL);val &= ~SOFTWARE_EN;writel_relaxed(val, dfi_regs + DDRMON_CTRL);+}
+static int rk3399_dmc_get_busier_ch(struct device *dev) +{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);u32 tmp, max = 0;u32 i, busier_ch = 0;void __iomem *dfi_regs = dmcfreq->regs;rk3399_dmc_stop_hardware_counter(dev);/* Find out which channel is busier */for (i = 0; i < RK3399_DMC_NUM_CH; i++) {dmcfreq->ch_usage[i].access = readl_relaxed(dfi_regs +DDRMON_CH0_DFI_ACCESS_NUM + i * 20);dmcfreq->ch_usage[i].total = readl_relaxed(dfi_regs +DDRMON_CH0_COUNT_NUM + i * 20);tmp = dmcfreq->ch_usage[i].access;if (tmp > max) {busier_ch = i;max = tmp;}}rk3399_dmc_start_hardware_counter(dev);return busier_ch;+}
+static int rk3399_dmcfreq_get_dev_status(struct device *dev,
struct devfreq_dev_status *stat)+{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);int busier_ch;busier_ch = rk3399_dmc_get_busier_ch(dev);stat->current_frequency = dmcfreq->rate;stat->busy_time = dmcfreq->ch_usage[busier_ch].access;stat->total_time = dmcfreq->ch_usage[busier_ch].total;return 0;+}
+static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq) +{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);*freq = dmcfreq->rate;return 0;+}
+static void rk3399_dmcfreq_exit(struct device *dev) +{
struct platform_device *pdev = container_of(dev, struct platform_device,dev);struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);devfreq_unregister_opp_notifier(dev, dmcfreq->devfreq);+}
+static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
.polling_ms = 200,.target = rk3399_dmcfreq_target,.get_dev_status = rk3399_dmcfreq_get_dev_status,.get_cur_freq = rk3399_dmcfreq_get_cur_freq,.exit = rk3399_dmcfreq_exit,+};
+static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev) +{
rockchip_dmc_disable();return 0;+}
+static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev) +{
rockchip_dmc_enable();return 0;+}
+static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
rk3399_dmcfreq_resume);+static int rk3399_dmc_enable_notify(struct notifier_block *nb,
unsigned long event, void *data)+{
struct rk3399_dmcfreq *dmcfreq =container_of(nb, struct rk3399_dmcfreq, dmc_nb);unsigned long freq = ULONG_MAX;if (event == DMC_ENABLE) {devfreq_resume_device(dmcfreq->devfreq);rk3399_dmc_start_hardware_counter(dmcfreq->dev);return NOTIFY_OK;} else if (event == DMC_DISABLE) {devfreq_suspend_device(dmcfreq->devfreq);rk3399_dmc_stop_hardware_counter(dmcfreq->dev);/* when disable dmc, set sdram to max frequency */rk3399_dmcfreq_target(dmcfreq->dev, &freq, 0);return NOTIFY_OK;}return NOTIFY_DONE;+}
+static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id) +{
struct rk3399_dmcfreq *dmcfreq = dev_id;complete(&dmcfreq->dcf_hold_completion);return IRQ_HANDLED;+}
+static int rk3399_dmcfreq_probe(struct platform_device *pdev) +{
struct device *dev = &pdev->dev;struct rk3399_dmcfreq *data;struct resource *res;int ret, irq;struct device_node *np = pdev->dev.of_node, *node;irq = platform_get_irq(pdev, 0);if (irq < 0) {dev_err(&pdev->dev, "no dmc irq resource\n");return -EINVAL;}data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);if (!data)return -ENOMEM;mutex_init(&data->lock);res = platform_get_resource(pdev, IORESOURCE_MEM, 0);data->regs = devm_ioremap_resource(&pdev->dev, res);if (IS_ERR(data->regs))return PTR_ERR(data->regs);data->vdd_center = devm_regulator_get(dev, "center");if (IS_ERR(data->vdd_center)) {dev_err(dev, "Cannot get the regulator \"center\"\n");return PTR_ERR(data->vdd_center);}data->dmc_clk = devm_clk_get(dev, "dmc_clk");if (IS_ERR(data->dmc_clk)) {dev_err(dev, "Cannot get the clk dmc_clk\n");return PTR_ERR(data->dmc_clk);};/** We add a devfreq driver to our parent since it has a device tree node* with operating points.*/if (dev_pm_opp_of_add_table(dev)) {dev_err(dev, "Invalid operating-points in device tree.\n");return -EINVAL;}of_property_read_u32(np, "upthreshold",&data->ondemand_data.upthreshold);of_property_read_u32(np, "downdifferential",&data->ondemand_data.downdifferential);data->devfreq = devfreq_add_device(dev,&rk3399_devfreq_dmc_profile,"simple_ondemand",&data->ondemand_data);if (IS_ERR(data->devfreq))return PTR_ERR(data->devfreq);devfreq_register_opp_notifier(dev, data->devfreq);data->dmc_nb.notifier_call = rk3399_dmc_enable_notify;dmc_register_notifier(&data->dmc_nb);data->irq = irq;ret = devm_request_irq(dev, irq, rk3399_dmc_irq, IRQF_ONESHOT,dev_name(dev), data);if (ret) {dev_err(dev, "failed to request dmc irq: %d\n", ret);return ret;}init_completion(&data->dcf_hold_completion);/* try to find the optional reference to the pmu syscon */node = of_parse_phandle(np, "rockchip,pmu", 0);if (node) {data->regmap_pmu = syscon_node_to_regmap(node);if (IS_ERR(data->regmap_pmu))return PTR_ERR(data->regmap_pmu);}data->dev = dev;platform_set_drvdata(pdev, data);return 0;+}
+static int rk3399_dmcfreq_remove(struct platform_device *pdev) +{
struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);devfreq_remove_device(dmcfreq->devfreq);regulator_put(dmcfreq->vdd_center);return 0;+}
+static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
{ .compatible = "rockchip,rk3399-dmc" },{ },+};
+static struct platform_driver rk3399_dmcfreq_driver = {
.probe = rk3399_dmcfreq_probe,.remove = rk3399_dmcfreq_remove,.driver = {.name = "rk3399-dmc-freq",.pm = &rk3399_dmcfreq_pm,.of_match_table = rk3399dmc_devfreq_of_match,},+}; +module_platform_driver(rk3399_dmcfreq_driver);
+MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework"); diff --git a/drivers/devfreq/rockchip/rockchip_dmc.c b/drivers/devfreq/rockchip/rockchip_dmc.c new file mode 100644 index 0000000..ecc6598 --- /dev/null +++ b/drivers/devfreq/rockchip/rockchip_dmc.c @@ -0,0 +1,132 @@ +/*
- Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- Author: Lin Huang hl@rock-chips.com
- This program is free software; you can redistribute it and/or modify it
- under the terms and conditions of the GNU General Public License,
- version 2, as published by the Free Software Foundation.
- This program is distributed in the hope it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
- */
+#include <linux/mutex.h> +#include <soc/rockchip/rockchip_dmc.h>
+static int num_wait; +static int num_disable; +static BLOCKING_NOTIFIER_HEAD(dmc_notifier_list); +static DEFINE_MUTEX(dmc_en_lock); +static DEFINE_MUTEX(dmc_sync_lock);
+void dmc_event(int event) +{
mutex_lock(&dmc_sync_lock);blocking_notifier_call_chain(&dmc_notifier_list, event, NULL);mutex_unlock(&dmc_sync_lock);+} +EXPORT_SYMBOL_GPL(dmc_event);
+/**
- rockchip_dmc_enabled - Returns true if dmc freq is enabled, false otherwise.
- */
+bool rockchip_dmc_enabled(void) +{
return num_disable <= 0 && num_wait <= 1;+} +EXPORT_SYMBOL_GPL(rockchip_dmc_enabled);
+/**
- rockchip_dmc_enable - Enable dmc frequency scaling. Will only enable
- frequency scaling if there are 1 or fewer notifiers. Call to undo
- rockchip_dmc_disable.
- */
+void rockchip_dmc_enable(void) +{
mutex_lock(&dmc_en_lock);num_disable--;WARN_ON(num_disable < 0);if (rockchip_dmc_enabled())dmc_event(DMC_ENABLE);mutex_unlock(&dmc_en_lock);+} +EXPORT_SYMBOL_GPL(rockchip_dmc_enable);
+/**
- rockchip_dmc_disable - Disable dmc frequency scaling. Call when something
- cannot coincide with dmc frequency scaling.
- */
+void rockchip_dmc_disable(void) +{
mutex_lock(&dmc_en_lock);if (rockchip_dmc_enabled())dmc_event(DMC_DISABLE);num_disable++;mutex_unlock(&dmc_en_lock);+} +EXPORT_SYMBOL_GPL(rockchip_dmc_disable);
+int dmc_register_notifier(struct notifier_block *nb) +{
int ret;if (!nb)return -EINVAL;ret = blocking_notifier_chain_register(&dmc_notifier_list, nb);return ret;+} +EXPORT_SYMBOL_GPL(dmc_register_notifier);
+int dmc_unregister_notifier(struct notifier_block *nb) +{
int ret;if (!nb)return -EINVAL;ret = blocking_notifier_chain_unregister(&dmc_notifier_list, nb);return ret;+} +EXPORT_SYMBOL_GPL(dmc_unregister_notifier);
+int rockchip_dmc_get(struct notifier_block *nb) +{
if (!nb)return -EINVAL;mutex_lock(&dmc_en_lock);/* if use two vop, need to disable dmc */if (num_wait == 1 && num_disable <= 0)dmc_event(DMC_DISABLE);num_wait++;dmc_register_notifier(nb);mutex_unlock(&dmc_en_lock);return 0;+} +EXPORT_SYMBOL_GPL(rockchip_dmc_get);
+int rockchip_dmc_put(struct notifier_block *nb) +{
if (!nb)return -EINVAL;mutex_lock(&dmc_en_lock);num_wait--;/* from 2 vop back to 1 vop, need enable dmc */if (num_wait == 1 && num_disable <= 0)dmc_event(DMC_ENABLE);dmc_unregister_notifier(nb);mutex_unlock(&dmc_en_lock);return 0;+} +EXPORT_SYMBOL_GPL(rockchip_dmc_put); diff --git a/include/soc/rockchip/rockchip_dmc.h b/include/soc/rockchip/rockchip_dmc.h new file mode 100644 index 0000000..6bb58d6 --- /dev/null +++ b/include/soc/rockchip/rockchip_dmc.h @@ -0,0 +1,44 @@ +/*
- Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
- This program is free software; you can redistribute it and/or modify it
- under the terms and conditions of the GNU General Public License,
- version 2, as published by the Free Software Foundation.
- This program is distributed in the hope it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
- */
+#ifndef __SOC_ROCKCHIP_DMC_H +#define __SOC_ROCKCHIP_DMC_H
+#include <linux/notifier.h>
+#define DMC_ENABLE 0 +#define DMC_DISABLE 1 +#define DMCFREQ_ADJUST 2 +#define DMCFREQ_FINISH 3
+#ifdef CONFIG_ARM_ROCKCHIP_DMC_DEVFREQ +int rockchip_dmc_get(struct notifier_block *nb); +int rockchip_dmc_put(struct notifier_block *nb); +#else +static inline int rockchip_dmc_get(struct notifier_block *nb) +{
return 0;+} +static inline int rockchip_dmc_put(struct notifier_block *nb) +{
return 0;+} +#endif
+void dmc_event(int event); +int dmc_register_notifier(struct notifier_block *nb); +int dmc_unregister_notifier(struct notifier_block *nb); +void rockchip_dmc_enable(void); +void rockchip_dmc_disable(void); +bool rockchip_dmc_enabled(void);
+#endif
1.9.1
when in ddr frequency scaling process, vop can not do enable or disable operate, since dcf will base on vop vblank time to do frequency scaling and need to get vop irq if there have vop enabled. So need register to dmc notifier, and we can get the dmc status.
Signed-off-by: Lin Huang hl@rock-chips.com --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 51 +++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 1c4d5b5..7ee0cd0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -31,6 +31,8 @@ #include <linux/reset.h> #include <linux/delay.h>
+#include <soc/rockchip/rockchip_dmc.h> + #include "rockchip_drm_drv.h" #include "rockchip_drm_gem.h" #include "rockchip_drm_fb.h" @@ -116,6 +118,9 @@ struct vop {
const struct vop_data *data;
+ struct notifier_block dmc_nb; + int dmc_in_process; + uint32_t *regsbak; void __iomem *regs;
@@ -426,14 +431,41 @@ static void vop_dsp_hold_valid_irq_disable(struct vop *vop) spin_unlock_irqrestore(&vop->irq_lock, flags); }
+static int dmc_notify(struct notifier_block *nb, unsigned long event, + void *data) +{ + struct vop *vop = container_of(nb, struct vop, dmc_nb); + + if (event == DMCFREQ_ADJUST) + vop->dmc_in_process = 1; + else if (event == DMCFREQ_FINISH) + vop->dmc_in_process = 0; + + return NOTIFY_OK; +} + static void vop_enable(struct drm_crtc *crtc) { struct vop *vop = to_vop(crtc); int ret; + int timeout_count = 500; + int timeout_loop = 0;
if (vop->is_enabled) return;
+ /* + * if in dmc scaling frequency process, wait until it finish + * use 100ms as timeout time. + */ + while (timeout_loop < timeout_count) { + if (vop->dmc_in_process == 0) + break; + + timeout_loop++; + usleep_range(150, 200); + } + ret = pm_runtime_get_sync(vop->dev); if (ret < 0) { dev_err(vop->dev, "failed to get pm runtime: %d\n", ret); @@ -485,6 +517,7 @@ static void vop_enable(struct drm_crtc *crtc) enable_irq(vop->irq);
drm_crtc_vblank_on(crtc); + rockchip_dmc_get(&vop->dmc_nb);
return;
@@ -500,11 +533,25 @@ static void vop_crtc_disable(struct drm_crtc *crtc) { struct vop *vop = to_vop(crtc); int i; + int timeout_count = 500; + int timeout_loop = 0;
if (!vop->is_enabled) return;
/* + * if in dmc scaling frequency process, wait until it finish + * use 100ms as timeout time. + */ + while (timeout_loop < timeout_count) { + if (vop->dmc_in_process == 0) + break; + + timeout_loop++; + usleep_range(150, 200); + } + + /* * We need to make sure that all windows are disabled before we * disable that crtc. Otherwise we might try to scan from a destroyed * buffer later. @@ -517,7 +564,7 @@ static void vop_crtc_disable(struct drm_crtc *crtc) VOP_WIN_SET(vop, win, enable, 0); spin_unlock(&vop->reg_lock); } - + rockchip_dmc_put(&vop->dmc_nb); drm_crtc_vblank_off(crtc);
/* @@ -1243,7 +1290,7 @@ static int vop_create_crtc(struct vop *vop) ret = -ENOENT; goto err_cleanup_crtc; } - + vop->dmc_nb.notifier_call = dmc_notify; init_completion(&vop->dsp_hold_completion); init_completion(&vop->wait_update_complete); crtc->port = port;
On Wed, Jun 1, 2016 at 2:35 AM, Lin Huang hl@rock-chips.com wrote:
when in ddr frequency scaling process, vop can not do enable or disable operate, since dcf will base on vop vblank time to do frequency scaling and need to get vop irq if there have vop enabled. So need register to dmc notifier, and we can get the dmc status.
Signed-off-by: Lin Huang hl@rock-chips.com
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 51 +++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 1c4d5b5..7ee0cd0 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -31,6 +31,8 @@ #include <linux/reset.h> #include <linux/delay.h>
+#include <soc/rockchip/rockchip_dmc.h>
#include "rockchip_drm_drv.h" #include "rockchip_drm_gem.h" #include "rockchip_drm_fb.h" @@ -116,6 +118,9 @@ struct vop {
const struct vop_data *data;
struct notifier_block dmc_nb;int dmc_in_process;uint32_t *regsbak; void __iomem *regs;@@ -426,14 +431,41 @@ static void vop_dsp_hold_valid_irq_disable(struct vop *vop) spin_unlock_irqrestore(&vop->irq_lock, flags); }
+static int dmc_notify(struct notifier_block *nb, unsigned long event,
void *data)+{
struct vop *vop = container_of(nb, struct vop, dmc_nb);if (event == DMCFREQ_ADJUST)vop->dmc_in_process = 1;else if (event == DMCFREQ_FINISH)vop->dmc_in_process = 0;return NOTIFY_OK;+}
static void vop_enable(struct drm_crtc *crtc) { struct vop *vop = to_vop(crtc); int ret;
int timeout_count = 500;int timeout_loop = 0; if (vop->is_enabled) return;/** if in dmc scaling frequency process, wait until it finish* use 100ms as timeout time.*/while (timeout_loop < timeout_count) {if (vop->dmc_in_process == 0)break;timeout_loop++;usleep_range(150, 200);}
wait_event with wake_up_all should work better here than using usleep_range.
ret = pm_runtime_get_sync(vop->dev); if (ret < 0) { dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);@@ -485,6 +517,7 @@ static void vop_enable(struct drm_crtc *crtc) enable_irq(vop->irq);
drm_crtc_vblank_on(crtc);
rockchip_dmc_get(&vop->dmc_nb); return;@@ -500,11 +533,25 @@ static void vop_crtc_disable(struct drm_crtc *crtc) { struct vop *vop = to_vop(crtc); int i;
int timeout_count = 500;int timeout_loop = 0; if (!vop->is_enabled) return; /** if in dmc scaling frequency process, wait until it finish* use 100ms as timeout time.*/while (timeout_loop < timeout_count) {if (vop->dmc_in_process == 0)break;timeout_loop++;usleep_range(150, 200);}/* * We need to make sure that all windows are disabled before we * disable that crtc. Otherwise we might try to scan from a destroyed * buffer later.@@ -517,7 +564,7 @@ static void vop_crtc_disable(struct drm_crtc *crtc) VOP_WIN_SET(vop, win, enable, 0); spin_unlock(&vop->reg_lock); }
rockchip_dmc_put(&vop->dmc_nb); drm_crtc_vblank_off(crtc); /*@@ -1243,7 +1290,7 @@ static int vop_create_crtc(struct vop *vop) ret = -ENOENT; goto err_cleanup_crtc; }
vop->dmc_nb.notifier_call = dmc_notify; init_completion(&vop->dsp_hold_completion); init_completion(&vop->wait_update_complete); crtc->port = port;-- 1.9.1
dri-devel@lists.freedesktop.org
-
Chanwoo Choi -
dbasehore . -
Doug Anderson -
Heiko Stübner -
hl -
Lin Huang
-
MyungJoo Ham