Hi, Yongqiang:

On Mon, 2021-04-12 at 15:25 +0800, Yongqiang Niu wrote:

the orginal formula will caused rdma fifo threshold config overflow

Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com

drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 728aaad..8c9371b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -167,7 +167,7 @@ void mtk_rdma_config(struct device *dev, unsigned int width, * output threshold to 6 microseconds with 7/6 overhead to * account for blanking, and with a pixel depth of 4 bytes: */

• threshold = width * height * vrefresh * 4 * 7 / 1000000;

• threshold = rdma_fifo_size * 7 / 10;

It's better to set threshold by width and height, but it seems that no one could come out a solution for all SoC. I could just accept this solution, but I need some addition comment for this solution. How do you decide 7/10? In the future, another may need to modify this value and he need to know why you use 7/10. If you just choose it at random, just tell us that you just randomly choose it.

Regards, CK

reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);