MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI, EDP etc. Add required DPU device tree bindings for SC7280.
Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com
Changes in v2: - Drop target from description (Stephen Boyd) - Drop items from compatible (Stephen Boyd) - Add clock names one per line for readability (Stephen Boyd) - Use correct indendation (Stephen Boyd) --- .../bindings/display/msm/dpu-sc7280.yaml | 232 +++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml new file mode 100644 index 0000000..fbeb931 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml @@ -0,0 +1,232 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/dpu-sc7280.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display DPU dt properties for SC7280 + +maintainers: + - Krishna Manikandan mkrishn@codeaurora.org + +description: | + Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS and DPU are mentioned for SC7280. + +properties: + compatible: + const: qcom,sc7280-mdss + + reg: + maxItems: 1 + + reg-names: + const: mdss + + power-domains: + maxItems: 1 + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock from dispcc + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#address-cells": true + + "#size-cells": true + + "#interrupt-cells": + const: 1 + + iommus: + items: + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 + + ranges: true + + interconnects: + items: + - description: Interconnect path specifying the port ids for data bus + + interconnect-names: + const: mdp0-mem + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + description: Node containing the properties of DPU. + + properties: + compatible: + const: qcom,sc7280-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display ahb clock + - description: Display lut clock + - description: Display core clock + - description: Display vsync clock + + clock-names: + items: + - const: bus + - const: nrt_bus + - const: iface + - const: lut + - const: core + - const: vsync + + interrupts: + maxItems: 1 + + power-domains: + maxItems: 1 + + operating-points-v2: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: | + Contains the list of output ports from DPU device. These ports + connect to interfaces that are external to the DPU hardware, + such as DSI, DP etc. Each output port contains an endpoint that + describes how it is connected to an external interface. + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF1 (DSI) + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: DPU_INTF5 (EDP) + + required: + - port@0 + + required: + - compatible + - reg + - reg-names + - clocks + - interrupts + - power-domains + - operating-points-v2 + - ports + +required: + - compatible + - reg + - reg-names + - power-domains + - clocks + - interrupts + - interrupt-controller + - iommus + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sc7280.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sc7280.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,sc7280-mdss"; + reg = <0xae00000 0x1000>; + reg-names = "mdss"; + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>; + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x900 0x402>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc7280-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&mdp_opp_table>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; + }; + }; + }; +...
Add mdss and mdp DT nodes for sc7280.
Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com
Changes in v2: - Rename display dt nodes (Stephen Boyd) - Add clock names one per line for readability (Stephen Boyd) --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 90 ++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d74a4c8..4ee7f2f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2588,6 +2588,96 @@ #power-domain-cells = <1>; };
+ mdss: display-subsystem@ae00000 { + compatible = "qcom,sc7280-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; + assigned-clock-rates = <300000000>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem"; + + iommus = <&apps_smmu 0x900 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdp: display-controller@ae01000 { + compatible = "qcom,sc7280-dpu"; + reg = <0 0x0ae01000 0 0x8f030>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>; + assigned-clock-rates = <300000000>, + <19200000>, + <19200000>; + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + status = "disabled"; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-380000000 { + opp-hz = /bits/ 64 <380000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-506666667 { + opp-hz = /bits/ 64 <506666667>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>;
Quoting Krishna Manikandan (2021-10-20 06:58:51)
Add mdss and mdp DT nodes for sc7280.
Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com
Changes in v2:
- Rename display dt nodes (Stephen Boyd)
- Add clock names one per line for readability (Stephen Boyd)
Reviewed-by: Stephen Boyd swboyd@chromium.org
Add DSI controller and PHY nodes for sc7280.
Signed-off-by: Rajeev Nandan quic_rajeevny@quicinc.com Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com Reviewed-by: Matthias Kaehlcke mka@chromium.org
Changes in v2: - Drop flags from interrupts (Stephen Boyd) - Rename dsi-opp-table (Stephen Boyd) - Rename dsi phy node (Stephen Boyd) --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 101 +++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 4ee7f2f..dd35882 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2652,6 +2652,18 @@
status = "disabled";
+ ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + mdp_opp_table: opp-table { compatible = "operating-points-v2";
@@ -2676,6 +2688,95 @@ }; }; }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + phys = <&dsi_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi_phy: phy@ae94400 { + compatible = "qcom,sc7280-dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; };
pdc: interrupt-controller@b220000 {
Quoting Krishna Manikandan (2021-10-20 06:58:52)
Add DSI controller and PHY nodes for sc7280.
Signed-off-by: Rajeev Nandan quic_rajeevny@quicinc.com Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com Reviewed-by: Matthias Kaehlcke mka@chromium.org
Changes in v2: - Drop flags from interrupts (Stephen Boyd) - Rename dsi-opp-table (Stephen Boyd) - Rename dsi phy node (Stephen Boyd)
Reviewed-by: Stephen Boyd swboyd@chromium.org
From: Sankeerth Billakanti quic_sbillaka@quicinc.com
Add edp controller and phy DT nodes for sc7280.
Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com
Changes in v2: - Move regulator definitions to board file (Matthias Kaehlcke) - Move the gpio definitions to board file (Matthias Kaehlcke) - Move the pinconf to board file (Matthias Kaehlcke) - Move status property (Stephen Boyd) - Drop flags from interrupts (Stephen Boyd) - Add clock names one per line for readability (Stephen Boyd) - Rename edp-opp-table (Stephen Boyd) --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 ++++++++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index dd35882..4450277 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2575,7 +2575,7 @@ reg = <0 0xaf00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <0>, <0>, <0>, <0>, <0>, <0>; + <0>, <0>, <0>, <0>, <&edp_phy 0>, <&edp_phy 1>; clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", @@ -2662,6 +2662,13 @@ remote-endpoint = <&dsi0_in>; }; }; + + port@1 { + reg = <1>; + dpu_intf5_out: endpoint { + remote-endpoint = <&edp_in>; + }; + }; };
mdp_opp_table: opp-table { @@ -2777,6 +2784,103 @@
status = "disabled"; }; + + msm_edp: edp@aea0000 { + compatible = "qcom,sc7280-edp"; + + reg = <0 0xaea0000 0 0x200>, + <0 0xaea0200 0 0x200>, + <0 0xaea0400 0 0xc00>, + <0 0xaea1000 0 0x400>; + + interrupt-parent = <&mdss>; + interrupts = <14>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, + <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; + clock-names = "core_xo", + "core_ref", + "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + #clock-cells = <1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, + <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; + assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; + + phys = <&edp_phy>; + phy-names = "dp"; + + operating-points-v2 = <&edp_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dpu_intf5_out>; + }; + }; + }; + + edp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-270000000 { + opp-hz = /bits/ 64 <270000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-540000000 { + opp-hz = /bits/ 64 <540000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + edp_phy: phy@aec2000 { + compatible = "qcom,sc7280-edp-phy"; + + reg = <0 0xaec2a00 0 0x19c>, + <0 0xaec2200 0 0xa0>, + <0 0xaec2600 0 0xa0>, + <0 0xaec2000 0 0x1c0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EDP_CLKREF_EN>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; };
pdc: interrupt-controller@b220000 { @@ -3932,6 +4036,7 @@ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; + };
cpu1-thermal {
Quoting Krishna Manikandan (2021-10-20 06:58:53)
From: Sankeerth Billakanti quic_sbillaka@quicinc.com
Add edp controller and phy DT nodes for sc7280.
Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com
Some comments below
Reviewed-by: Stephen Boyd swboyd@chromium.org
Changes in v2: - Move regulator definitions to board file (Matthias Kaehlcke) - Move the gpio definitions to board file (Matthias Kaehlcke) - Move the pinconf to board file (Matthias Kaehlcke) - Move status property (Stephen Boyd) - Drop flags from interrupts (Stephen Boyd) - Add clock names one per line for readability (Stephen Boyd) - Rename edp-opp-table (Stephen Boyd)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 ++++++++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index dd35882..4450277 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2575,7 +2575,7 @@ reg = <0 0xaf00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>,
<0>, <0>, <0>, <0>, <0>, <0>;
<0>, <0>, <0>, <0>, <&edp_phy 0>, <&edp_phy 1>;
I can already tell this is going to be a merge mess! Can this also be one cell per line?
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk",@@ -2777,6 +2784,103 @@
status = "disabled"; };
msm_edp: edp@aea0000 {compatible = "qcom,sc7280-edp";reg = <0 0xaea0000 0 0x200>,<0 0xaea0200 0 0x200>,<0 0xaea0400 0 0xc00>,<0 0xaea1000 0 0x400>;interrupt-parent = <&mdss>;interrupts = <14>;clocks = <&rpmhcc RPMH_CXO_CLK>,<&gcc GCC_EDP_CLKREF_EN>,<&dispcc DISP_CC_MDSS_AHB_CLK>,<&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,<&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,<&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;clock-names = "core_xo","core_ref","core_iface","core_aux","ctrl_link","ctrl_link_iface","stream_pixel";#clock-cells = <1>;assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;phys = <&edp_phy>;phy-names = "dp";operating-points-v2 = <&edp_opp_table>;power-domains = <&rpmhpd SC7280_CX>;#address-cells = <1>;#size-cells = <0>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;edp_in: endpoint {remote-endpoint = <&dpu_intf5_out>;};};};edp_opp_table: opp-table {compatible = "operating-points-v2";opp-160000000 {opp-hz = /bits/ 64 <160000000>;required-opps = <&rpmhpd_opp_low_svs>;};opp-270000000 {opp-hz = /bits/ 64 <270000000>;required-opps = <&rpmhpd_opp_svs>;};opp-540000000 {opp-hz = /bits/ 64 <540000000>;required-opps = <&rpmhpd_opp_nom>;};opp-810000000 {opp-hz = /bits/ 64 <810000000>;required-opps = <&rpmhpd_opp_nom>;};};};edp_phy: phy@aec2000 {
unit address needs to match first reg property. This should be
edp_phy: phy@aec2a00
compatible = "qcom,sc7280-edp-phy";reg = <0 0xaec2a00 0 0x19c>,<0 0xaec2200 0 0xa0>,<0 0xaec2600 0 0xa0>,<0 0xaec2000 0 0x1c0>;clocks = <&rpmhcc RPMH_CXO_CLK>,<&gcc GCC_EDP_CLKREF_EN>;clock-names = "aux","cfg_ahb";#clock-cells = <1>;#phy-cells = <0>;status = "disabled";}; }; pdc: interrupt-controller@b220000 {@@ -3932,6 +4036,7 @@ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; };
Drop this?
On 2021-10-21 11:44, Stephen Boyd wrote:
Quoting Krishna Manikandan (2021-10-20 06:58:53)
From: Sankeerth Billakanti quic_sbillaka@quicinc.com
Add edp controller and phy DT nodes for sc7280.
Signed-off-by: Sankeerth Billakanti quic_sbillaka@quicinc.com Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com
Some comments below
Reviewed-by: Stephen Boyd swboyd@chromium.org
Changes in v2: - Move regulator definitions to board file (Matthias Kaehlcke) - Move the gpio definitions to board file (Matthias Kaehlcke) - Move the pinconf to board file (Matthias Kaehlcke) - Move status property (Stephen Boyd) - Drop flags from interrupts (Stephen Boyd) - Add clock names one per line for readability (Stephen Boyd) - Rename edp-opp-table (Stephen Boyd)
arch/arm64/boot/dts/qcom/sc7280.dtsi | 107 ++++++++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index dd35882..4450277 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2575,7 +2575,7 @@ reg = <0 0xaf00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>,
<0>, <0>, <0>, <0>, <0>, <0>;
<0>, <0>, <0>, <0>, <&edp_phy 0>,<&edp_phy 1>;
I can already tell this is going to be a merge mess! Can this also be one cell per line?
where are dsi phy? (<&dsi_phy 0>, <&dsi_phy 1>)
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk",@@ -2777,6 +2784,103 @@
status = "disabled"; };
msm_edp: edp@aea0000 {compatible = "qcom,sc7280-edp";reg = <0 0xaea0000 0 0x200>,<0 0xaea0200 0 0x200>,<0 0xaea0400 0 0xc00>,<0 0xaea1000 0 0x400>;interrupt-parent = <&mdss>;interrupts = <14>;clocks = <&rpmhcc RPMH_CXO_CLK>,<&gcc GCC_EDP_CLKREF_EN>,<&dispccDISP_CC_MDSS_AHB_CLK>,
<&dispccDISP_CC_MDSS_EDP_AUX_CLK>,
<&dispccDISP_CC_MDSS_EDP_LINK_CLK>,
<&dispccDISP_CC_MDSS_EDP_LINK_INTF_CLK>,
<&dispccDISP_CC_MDSS_EDP_PIXEL_CLK>;
clock-names = "core_xo","core_ref","core_iface","core_aux","ctrl_link","ctrl_link_iface","stream_pixel";#clock-cells = <1>;assigned-clocks = <&dispccDISP_CC_MDSS_EDP_LINK_CLK_SRC>,
<&dispccDISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
assigned-clock-parents = <&edp_phy 0>,<&edp_phy 1>;
phys = <&edp_phy>;phy-names = "dp";operating-points-v2 =<&edp_opp_table>;
power-domains = <&rpmhpd SC7280_CX>;#address-cells = <1>;#size-cells = <0>;status = "disabled";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;edp_in: endpoint {remote-endpoint = <&dpu_intf5_out>;
};};};edp_opp_table: opp-table {compatible ="operating-points-v2";
opp-160000000 {opp-hz = /bits/ 64<160000000>;
required-opps =<&rpmhpd_opp_low_svs>;
};opp-270000000 {opp-hz = /bits/ 64<270000000>;
required-opps =<&rpmhpd_opp_svs>;
};opp-540000000 {opp-hz = /bits/ 64<540000000>;
required-opps =<&rpmhpd_opp_nom>;
};opp-810000000 {opp-hz = /bits/ 64<810000000>;
required-opps =<&rpmhpd_opp_nom>;
};};};edp_phy: phy@aec2000 {unit address needs to match first reg property. This should be
edp_phy: phy@aec2a00
compatible = "qcom,sc7280-edp-phy";reg = <0 0xaec2a00 0 0x19c>,<0 0xaec2200 0 0xa0>,<0 0xaec2600 0 0xa0>,<0 0xaec2000 0 0x1c0>;clocks = <&rpmhcc RPMH_CXO_CLK>,<&gcc GCC_EDP_CLKREF_EN>;clock-names = "aux","cfg_ahb";#clock-cells = <1>;#phy-cells = <0>;status = "disabled";}; }; pdc: interrupt-controller@b220000 {@@ -3932,6 +4036,7 @@ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; };
Drop this?
Quoting Krishna Manikandan (2021-10-20 06:58:50)
MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU display controller, DSI, EDP etc. Add required DPU device tree bindings for SC7280.
Signed-off-by: Krishna Manikandan quic_mkrishn@quicinc.com
Changes in v2:
- Drop target from description (Stephen Boyd)
- Drop items from compatible (Stephen Boyd)
- Add clock names one per line for readability (Stephen Boyd)
- Use correct indendation (Stephen Boyd)
This changelog should come after the triple dash. qcom maintainers don't want drm style changelogs in the commit text.
Reviewed-by: Stephen Boyd swboyd@chromium.org
dri-devel@lists.freedesktop.org
-
khsieh＠codeaurora.org -
Krishna Manikandan -
Stephen Boyd