Hi Chun-Kuang,

Thanks for the review.

On Sat, 2021-10-16 at 07:37 +0800, Chun-Kuang Hu wrote:

Hi, Nancy:

Nancy.Lin nancy.lin@mediatek.com 於 2021年10月4日 週一 下午2:21寫道：

...

Add vdosys1 ETHDR definition.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

.../display/mediatek/mediatek,ethdr.yaml | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.y aml

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr .yaml new file mode 100644 index 000000000000..e127f0b392d0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr .yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/m...

+$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;...

+title: Mediatek Ethdr Device Tree Bindings

+maintainers:

• • Chun-Kuang Hu chunkuang.hu@kernel.org
• • Philipp Zabel p.zabel@pengutronix.de

+description: |

• ETHDR is designed for HDR video and graphics conversion in the

external display path.

• It handles multiple HDR input types and performs tone mapping,

color space/color

• format conversion, and then combine different layers, output the

required HDR or

• SDR signal to the subsequent display path. This engine is

composed of two video

• frontends, two graphic frontends, one video backend and a mixer.

+properties:

• compatible:
• items:

•  - const: mediatek,mt8195-disp-ethdr
  

• reg:
• maxItems: 7
• reg-names:
• items:

•  - const: mixer
  

•  - const: vdo_fe0
  

•  - const: vdo_fe1
  

•  - const: gfx_fe0
  

•  - const: gfx_fe1
  

•  - const: vdo_be
  

•  - const: adl_ds
  

• interrupts:
• minItems: 1
• iommus:
• description: The compatible property is DMA function blocks.

•  Should point to the respective IOMMU block with master port
  

as argument,

•  see
  

Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for

•  details.
  

In description, you does not mention that ethdr has dma function. I expect that video front end and graphics front end direct link to another hardware function block and no dma function. If it has both direct link and dma function, add explain in description.

There is DMA hardware inside the ETHDR engine, which are DS and ADL. The two engines can read hardware reg settings from dram and then apply the settings during the v-blanking period.

I will explain it in description.

Regards, Nancy

...

• minItems: 1
• maxItems: 2
• clocks:
• items:

•  - description: mixer clock
  

•  - description: video frontend 0 clock
  

•  - description: video frontend 1 clock
  

•  - description: graphic frontend 0 clock
  

•  - description: graphic frontend 1 clock
  

•  - description: video backend clock
  

•  - description: autodownload and menuload clock
  

•  - description: video frontend 0 async clock
  

•  - description: video frontend 1 async clock
  

•  - description: graphic frontend 0 async clock
  

•  - description: graphic frontend 1 async clock
  

•  - description: video backend async clock
  

•  - description: ethdr top clock
  

• clock-names:
• items:

•  - const: mixer
  

•  - const: vdo_fe0
  

•  - const: vdo_fe1
  

•  - const: gfx_fe0
  

•  - const: gfx_fe1
  

•  - const: vdo_be
  

•  - const: adl_ds
  

•  - const: vdo_fe0_async
  

•  - const: vdo_fe1_async
  

•  - const: gfx_fe0_async
  

•  - const: gfx_fe1_async
  

•  - const: vdo_be_async
  

•  - const: ethdr_top
  

• power-domains:
• maxItems: 1
• resets:
• maxItems: 5
• mediatek,gce-client-reg:
• $ref: /schemas/types.yaml#/definitions/phandle-array
• description: The register of display function block to be set

by gce.

•  There are 4 arguments in this property, gce node, subsys id,
  

offset and

•  register size. The subsys id is defined in the gce header of
  

each chips

•  include/include/dt-bindings/gce/<chip>-gce.h, mapping to the
  

register of

•  display function block.
  

+required:

• • compatible
• • reg
• • clocks
• • clock-names
• • interrupts
• • power-domains

+additionalProperties: false

+examples:

• • |
• disp_ethdr@1c114000 {

•        compatible = "mediatek,mt8195-disp-ethdr";
  

•        reg = <0 0x1c114000 0 0x1000>,
  

•              <0 0x1c115000 0 0x1000>,
  

•              <0 0x1c117000 0 0x1000>,
  

•              <0 0x1c119000 0 0x1000>,
  

•              <0 0x1c11A000 0 0x1000>,
  

•              <0 0x1c11B000 0 0x1000>,
  

•              <0 0x1c11C000 0 0x1000>;
  

•        reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0",
  

"gfx_fe1",

•                    "vdo_be", "adl_ds";
  

•        mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX
  

0x4000 0x1000>,

•                                  <&gce1 SUBSYS_1c11XXXX
  

0x5000 0x1000>,

•                                  <&gce1 SUBSYS_1c11XXXX
  

0x7000 0x1000>,

•                                  <&gce1 SUBSYS_1c11XXXX
  

0x9000 0x1000>,

•                                  <&gce1 SUBSYS_1c11XXXX
  

0xA000 0x1000>,

•                                  <&gce1 SUBSYS_1c11XXXX
  

0xB000 0x1000>,

•                                  <&gce1 SUBSYS_1c11XXXX
  

0xC000 0x1000>;

•        clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
  

•                 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
  

•                 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
  

•                 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
  

•                 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
  

•                 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
  

•                 <&vdosys1 CLK_VDO1_26M_SLOW>,
  

•                 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
  

•                 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
  

•                 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
  

•                 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
  

•                 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
  

•                 <&topckgen CLK_TOP_ETHDR_SEL>;
  

•        clock-names = "mixer", "vdo_fe0", "vdo_fe1",
  

"gfx_fe0", "gfx_fe1",

•                      "vdo_be", "adl_ds", "vdo_fe0_async",
  

"vdo_fe1_async",

•                      "gfx_fe0_async",
  

"gfx_fe1_async","vdo_be_async",

•                      "ethdr_top";
  

•        power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
  

•        iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
  

•                 <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
  

•        interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /*
  

disp mixer */

•        resets = <&vdosys1
  

MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,

•                 <&vdosys1
  

MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,

•                 <&vdosys1
  

MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,

•                 <&vdosys1
  

MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,

•                 <&vdosys1
  

MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;

• };

+...

2.18.0

Hi, Nancy:

Nancy.Lin nancy.lin@mediatek.com 於 2021年10月4日 週一 下午2:21寫道：

Add vdosys1 reset control bit for MT8195 platform.

Reviewed-by: Chun-Kuang Hu chunkuang.hu@kernel.org

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

include/dt-bindings/reset/mt8195-resets.h | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h index a26bccc8b957..aab8d74496a6 100644 --- a/include/dt-bindings/reset/mt8195-resets.h +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -26,4 +26,16 @@

#define MT8195_TOPRGU_SW_RST_NUM 16

+/* VDOSYS1 */ +#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28 +#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54 +#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55

#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */

2.18.0

Hi Angelo,

Thanks for the review.

On Thu, 2021-10-14 at 16:56 +0200, AngeloGioacchino Del Regno wrote:

Il 04/10/21 08:21, Nancy.Lin ha scritto:

...

MT8195 vdosys1 has more than 32 reset bits and a different reset base than other chips. Modify mmsys for support 64 bit and different reset base.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/soc/mediatek/mt8195-mmsys.h | 1 + drivers/soc/mediatek/mtk-mmsys.c | 21 ++++++++++++++++----- drivers/soc/mediatek/mtk-mmsys.h | 2 ++ 3 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h index 648baaec112b..f67801c42fd9 100644 --- a/drivers/soc/mediatek/mt8195-mmsys.h +++ b/drivers/soc/mediatek/mt8195-mmsys.h @@ -123,6 +123,7 @@ #define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68 #define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)

+#define MT8195_VDO1_SW0_RST_B 0x1d0

All other definitions are indented with tabulations, but these are spaces here. Please, do not mix formatting.

Regards,

• Angelo

OK, I will fix it.

Regards, Nancy

Add mtk-mutex support for mt8195 vdosys1. The vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. Ovl_adaptor is composed of several sub-elements, so change it to support multi-bit control.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/soc/mediatek/mtk-mutex.c | 296 ++++++++++++++++++------------- 1 file changed, 175 insertions(+), 121 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 36502b27fe20..7767fedbd14f 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -29,113 +29,142 @@

#define INT_MUTEX BIT(1)

-#define MT8167_MUTEX_MOD_DISP_PWM 1

This patch doesn't only add support for MT8195 vdosys1, but also changes all definitions to a different "format", and also changes the type for "mutex_mod" from int to long. In reality, the actual functional change is minimal, compared to the size of this entire patch.

Please, split this patch in two parts: one patch changing the defines and the mutex_mod type (specifying that it's a preparation for adding support for mt8195 vdosys1 mutex) and one patch adding such support.

Thanks!

Regards, - Angelo

Hi Chun-Kuang,

Thanks for the review.

On Wed, 2021-10-20 at 00:38 +0800, Chun-Kuang Hu wrote:

Hi, Nancy:

Nancy.Lin nancy.lin@mediatek.com 於 2021年10月4日 週一 下午2:21寫道：

...

Add MDP_RDMA driver for MT8195. MDP_RDMA is the DMA engine of the ovl_adaptor component.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/gpu/drm/mediatek/Makefile | 3 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 7 + drivers/gpu/drm/mediatek/mtk_mdp_rdma.c | 305 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_mdp_rdma.h | 19 ++ 4 files changed, 333 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.c create mode 100644 drivers/gpu/drm/mediatek/mtk_mdp_rdma.h

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index a38e88e82d12..6e604a933ed0 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -13,7 +13,8 @@ mediatek-drm-y := mtk_disp_aal.o \ mtk_drm_gem.o \ mtk_drm_plane.o \ mtk_dsi.o \

•             mtk_dpi.o
  

•             mtk_dpi.o \
  

•             mtk_mdp_rdma.o
  
  

obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index a33b13fe2b6e..b3a372cab0bd 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -8,6 +8,7 @@

#include <linux/soc/mediatek/mtk-cmdq.h> #include "mtk_drm_plane.h" +#include "mtk_mdp_rdma.h"

int mtk_aal_clk_enable(struct device *dev); void mtk_aal_clk_disable(struct device *dev); @@ -106,4 +107,10 @@ void mtk_rdma_enable_vblank(struct device *dev, void *vblank_cb_data); void mtk_rdma_disable_vblank(struct device *dev);

+int mtk_mdp_rdma_clk_enable(struct device *dev); +void mtk_mdp_rdma_clk_disable(struct device *dev); +void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt); +void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt); +void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,

•                    struct cmdq_pkt *cmdq_pkt);
  

#endif diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c new file mode 100644 index 000000000000..d05b1ef976bc --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#include <drm/drm_fourcc.h> +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/soc/mediatek/mtk-cmdq.h>

+#include "mtk_drm_drv.h" +#include "mtk_disp_drv.h"

Alphabetic order.

OK.

...

+#include "mtk_mdp_rdma.h"

+#define MDP_RDMA_EN 0x000 +#define FLD_ROT_ENABLE BIT(0)

Use one 'tab' to replace 8 space.

OK.

...

+#define MDP_RDMA_RESET 0x008 +#define MDP_RDMA_CON 0x020 +#define FLD_OUTPUT_10B BIT(5) +#define FLD_SIMPLE_MODE BIT(4) +#define MDP_RDMA_GMCIF_CON 0x028 +#define FLD_COMMAND_DIV BIT(0) +#define FLD_EXT_PREULTRA_EN BIT(3) +#define FLD_RD_REQ_TYPE GENMASK(7, 4) +#define VAL_RD_REQ_TYPE_BURST_8_ACCESS 7 +#define FLD_ULTRA_EN GENMASK(13, 12) +#define VAL_ULTRA_EN_ENABLE 1 +#define FLD_PRE_ULTRA_EN GENMASK(17, 16) +#define VAL_PRE_ULTRA_EN_ENABLE 1 +#define FLD_EXT_ULTRA_EN BIT(18) +#define MDP_RDMA_SRC_CON 0x030 +#define FLD_OUTPUT_ARGB BIT(25) +#define FLD_BIT_NUMBER GENMASK(19, 18) +#define FLD_SWAP BIT(14) +#define FLD_UNIFORM_CONFIG BIT(17) +#define RDMA_INPUT_10BIT BIT(18) +#define FLD_SRC_FORMAT GENMASK(3, 0) +#define MDP_RDMA_COMP_CON 0x038 +#define FLD_AFBC_EN BIT(22) +#define FLD_AFBC_YUV_TRANSFORM BIT(21) +#define FLD_UFBDC_EN BIT(12) +#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060 +#define FLD_MF_BKGD_WB GENMASK(22, 0) +#define MDP_RDMA_MF_SRC_SIZE 0x070 +#define FLD_MF_SRC_H GENMASK(30, 16) +#define FLD_MF_SRC_W GENMASK(14, 0) +#define MDP_RDMA_MF_CLIP_SIZE 0x078 +#define FLD_MF_CLIP_H GENMASK(30, 16) +#define FLD_MF_CLIP_W GENMASK(14, 0) +#define MDP_RDMA_SRC_OFFSET_0 0x118 +#define FLD_SRC_OFFSET_0 GENMASK(31, 0) +#define MDP_RDMA_TRANSFORM_0 0x200 +#define FLD_INT_MATRIX_SEL GENMASK(27, 23) +#define FLD_TRANS_EN BIT(16) +#define MDP_RDMA_SRC_BASE_0 0xf00 +#define FLD_SRC_BASE_0 GENMASK(31, 0)

+#define RDMA_CSC_FULL709_TO_RGB 5

+enum rdma_format {

•   RDMA_INPUT_FORMAT_RGB565 = 0,
  

•   RDMA_INPUT_FORMAT_RGB888 = 1,
  

•   RDMA_INPUT_FORMAT_RGBA8888 = 2,
  

•   RDMA_INPUT_FORMAT_ARGB8888 = 3,
  

•   RDMA_INPUT_FORMAT_UYVY = 4,
  

•   RDMA_INPUT_FORMAT_YUY2 = 5,
  

•   RDMA_INPUT_FORMAT_Y8 = 7,
  

•   RDMA_INPUT_FORMAT_YV12 = 8,
  

•   RDMA_INPUT_FORMAT_UYVY_3PL = 9,
  

•   RDMA_INPUT_FORMAT_NV12 = 12,
  

•   RDMA_INPUT_FORMAT_UYVY_2PL = 13,
  

•   RDMA_INPUT_FORMAT_Y410 = 14
  

+};

+struct mtk_mdp_rdma {

•   void __iomem *regs;
  

•   struct clk *clk;
  

•   struct cmdq_client_reg          cmdq_reg;
  

Align indent of members.

OK.

...

+};

+static unsigned int rdma_fmt_convert(unsigned int fmt) +{

•   switch (fmt) {
  

•   default:
  

•   case DRM_FORMAT_RGB565:
  

•           return RDMA_INPUT_FORMAT_RGB565;
  

•   case DRM_FORMAT_BGR565:
  

•           return RDMA_INPUT_FORMAT_RGB565 | FLD_SWAP;
  

•   case DRM_FORMAT_RGB888:
  

•           return RDMA_INPUT_FORMAT_RGB888;
  

•   case DRM_FORMAT_BGR888:
  

•           return RDMA_INPUT_FORMAT_RGB888 | FLD_SWAP;
  

•   case DRM_FORMAT_RGBX8888:
  

•   case DRM_FORMAT_RGBA8888:
  

•           return RDMA_INPUT_FORMAT_ARGB8888;
  

•   case DRM_FORMAT_BGRX8888:
  

•   case DRM_FORMAT_BGRA8888:
  

•           return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP;
  

•   case DRM_FORMAT_XRGB8888:
  

•   case DRM_FORMAT_ARGB8888:
  

•           return RDMA_INPUT_FORMAT_RGBA8888;
  

•   case DRM_FORMAT_XBGR8888:
  

•   case DRM_FORMAT_ABGR8888:
  

•           return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP;
  

•   case DRM_FORMAT_ABGR2101010:
  

•           return RDMA_INPUT_FORMAT_RGBA8888 | FLD_SWAP |
  

RDMA_INPUT_10BIT;

•   case DRM_FORMAT_ARGB2101010:
  

•           return RDMA_INPUT_FORMAT_RGBA8888 |
  

RDMA_INPUT_10BIT;

•   case DRM_FORMAT_RGBA1010102:
  

•           return RDMA_INPUT_FORMAT_ARGB8888 | FLD_SWAP |
  

RDMA_INPUT_10BIT;

•   case DRM_FORMAT_BGRA1010102:
  

•           return RDMA_INPUT_FORMAT_ARGB8888 |
  

RDMA_INPUT_10BIT;

•   case DRM_FORMAT_UYVY:
  

•           return RDMA_INPUT_FORMAT_UYVY;
  

•   case DRM_FORMAT_YUYV:
  

•           return RDMA_INPUT_FORMAT_YUY2;
  

•   }
  

+}

+static void mtk_mdp_rdma_fifo_config(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{

•   struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
  

•   mtk_ddp_write_mask(cmdq_pkt, FLD_EXT_ULTRA_EN |
  

VAL_PRE_ULTRA_EN_ENABLE << 16 |

•                      VAL_ULTRA_EN_ENABLE << 12 |
  

VAL_RD_REQ_TYPE_BURST_8_ACCESS << 4 |

•                      FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV,
  

&priv->cmdq_reg,

•                      priv->regs, MDP_RDMA_GMCIF_CON,
  

FLD_EXT_ULTRA_EN |

•                      FLD_PRE_ULTRA_EN | FLD_ULTRA_EN |
  

FLD_RD_REQ_TYPE |

•                      FLD_EXT_PREULTRA_EN | FLD_COMMAND_DIV);
  

+}

+void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{

•   struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
  

•   mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv-
  

...

cmdq_reg,

•                      priv->regs, MDP_RDMA_EN,
  

FLD_ROT_ENABLE); +}

+void mtk_mdp_rdma_stop(struct device *dev, struct cmdq_pkt *cmdq_pkt) +{

•   struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
  

•   mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
  

•                      priv->regs, MDP_RDMA_EN,
  

FLD_ROT_ENABLE);

•   mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
  

MDP_RDMA_RESET);

•   mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
  

MDP_RDMA_RESET); +}

+void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,

•                    struct cmdq_pkt *cmdq_pkt)
  

+{

•   struct mtk_mdp_rdma *priv = dev_get_drvdata(dev);
  

•   const struct drm_format_info *fmt_info =
  

drm_format_info(cfg->fmt);

•   bool csc_enable = fmt_info->is_yuv ? true : false;
  

•   unsigned int src_pitch_y = cfg->pitch;
  

•   unsigned int bpp_y = fmt_info->cpp[0] * 8;
  

•   unsigned int offset_y = 0;
  

•   mtk_mdp_rdma_fifo_config(dev, cmdq_pkt);
  

•   mtk_ddp_write_mask(cmdq_pkt, FLD_UNIFORM_CONFIG, &priv-
  

...

cmdq_reg, priv->regs,

•                      MDP_RDMA_SRC_CON, FLD_UNIFORM_CONFIG);
  

•   mtk_ddp_write_mask(cmdq_pkt, rdma_fmt_convert(cfg->fmt),
  

&priv->cmdq_reg, priv->regs,

•                      MDP_RDMA_SRC_CON, FLD_SWAP |
  

FLD_SRC_FORMAT | FLD_BIT_NUMBER);

•   if (!csc_enable && fmt_info->has_alpha)
  

•           mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB,
  

&priv->cmdq_reg,

•                              priv->regs, MDP_RDMA_SRC_CON,
  

FLD_OUTPUT_ARGB);

•   else
  

•           mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg,
  

priv->regs,

•                              MDP_RDMA_SRC_CON,
  

FLD_OUTPUT_ARGB);

•   mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg,
  

priv->regs,

•                      MDP_RDMA_SRC_BASE_0, FLD_SRC_BASE_0);
  

•   mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg,
  

priv->regs,

•                      MDP_RDMA_MF_BKGD_SIZE_IN_BYTE,
  

FLD_MF_BKGD_WB);

•   mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv-
  

...

regs, MDP_RDMA_COMP_CON,

•                      FLD_AFBC_YUV_TRANSFORM | FLD_UFBDC_EN |
  

FLD_AFBC_EN);

•   mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv-
  

...

cmdq_reg, priv->regs,

•                      MDP_RDMA_CON, FLD_OUTPUT_10B);
  

•   mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv-
  

...

cmdq_reg, priv->regs,

•                      MDP_RDMA_CON, FLD_SIMPLE_MODE);
  

•   mtk_ddp_write_mask(cmdq_pkt, csc_enable << 16, &priv-
  

...

cmdq_reg, priv->regs,

•                      MDP_RDMA_TRANSFORM_0, FLD_TRANS_EN);
  

•   mtk_ddp_write_mask(cmdq_pkt, RDMA_CSC_FULL709_TO_RGB << 23,
  

&priv->cmdq_reg, priv->regs,

•                      MDP_RDMA_TRANSFORM_0,
  

FLD_INT_MATRIX_SEL);

In mtk_plane_update_new_state(), new_state->color_encoding has the information that non-RBG color is BT601, BT709, or BT2020.

OK, I will add color encoding info for color space convert.

...

•   offset_y  = (cfg->x_left * bpp_y >> 3) + cfg->y_top *
  

src_pitch_y;

Drop bpp_y, and

offset_y = cfg->x_left * fmt_info->cpp[0] + cfg->y_top * src_pitch_y;

OK.

...

•   mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg,
  

priv->regs,

•                      MDP_RDMA_SRC_OFFSET_0,
  

FLD_SRC_OFFSET_0);

•   mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg,
  

priv->regs,

•                      MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_W);
  

•   mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv-
  

...

cmdq_reg, priv->regs,

•                      MDP_RDMA_MF_SRC_SIZE, FLD_MF_SRC_H);
  

•   mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg,
  

priv->regs,

•                      MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_W);
  

If x_left > 0, CLIP_W could still be set to width?

...

•   mtk_ddp_write_mask(cmdq_pkt, cfg->height << 16, &priv-
  

...

cmdq_reg, priv->regs,

•                      MDP_RDMA_MF_CLIP_SIZE, FLD_MF_CLIP_H);
  

If y_top > 0, CLIP_H could still be set to height?

The parameters (x_left, y_top, width, height) in mtk_mdp_rdma_cfg struct means: rdma read data from frame buffer base addr offset (x_left, y_top) with size (width, height). The parameters (width, height) is not the source image size but the real size that RDMA want to read.

...

+}

+int mtk_mdp_rdma_clk_enable(struct device *dev) +{

•   struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
  

•   pm_runtime_get_sync(dev);
  

Align with other sub driver, pm runtime control is in mtk_drm_crtc.c

OK, I will move the pm runtime control to ovl_adaptor.

...

•   clk_prepare_enable(rdma->clk);
  

•   return 0;
  

+}

+void mtk_mdp_rdma_clk_disable(struct device *dev) +{

•   struct mtk_mdp_rdma *rdma = dev_get_drvdata(dev);
  

•   clk_disable_unprepare(rdma->clk);
  

•   pm_runtime_put(dev);
  

Ditto.

Regards, Chun-Kuang.

Regards, Nancy

...

+}

+static int mtk_mdp_rdma_bind(struct device *dev, struct device *master,

•                        void *data)
  

+{

•   return 0;
  

+}

+static void mtk_mdp_rdma_unbind(struct device *dev, struct device *master,

•                           void *data)
  

+{ +}

+static const struct component_ops mtk_mdp_rdma_component_ops = {

•   .bind   = mtk_mdp_rdma_bind,
  

•   .unbind = mtk_mdp_rdma_unbind,
  

+};

+static int mtk_mdp_rdma_probe(struct platform_device *pdev) +{

•   struct device *dev = &pdev->dev;
  

•   struct resource *res;
  

•   struct mtk_mdp_rdma *priv;
  

•   int ret = 0;
  

•   priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  

•   if (!priv)
  

•           return -ENOMEM;
  

•   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  

•   priv->regs = devm_ioremap_resource(dev, res);
  

•   if (IS_ERR(priv->regs)) {
  

•           dev_err(dev, "failed to ioremap rdma\n");
  

•           return PTR_ERR(priv->regs);
  

•   }
  

•   priv->clk = devm_clk_get(dev, NULL);
  

•   if (IS_ERR(priv->clk)) {
  

•           dev_err(dev, "failed to get rdma clk\n");
  

•           return PTR_ERR(priv->clk);
  

•   }
  

+#if IS_REACHABLE(CONFIG_MTK_CMDQ)

•   ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
  

•   if (ret)
  

•           dev_dbg(dev, "get mediatek,gce-client-reg
  

fail!\n"); +#endif

•   platform_set_drvdata(pdev, priv);
  

•   pm_runtime_enable(dev);
  

•   ret = component_add(dev, &mtk_mdp_rdma_component_ops);
  

•   if (ret != 0) {
  

•           pm_runtime_disable(dev);
  

•           dev_err(dev, "Failed to add component: %d\n", ret);
  

•   }
  

•   return ret;
  

+}

+static int mtk_mdp_rdma_remove(struct platform_device *pdev) +{

•   component_del(&pdev->dev, &mtk_mdp_rdma_component_ops);
  

•   pm_runtime_disable(&pdev->dev);
  

•   return 0;
  

+}

+static const struct of_device_id mtk_mdp_rdma_driver_dt_match[] = {

•   { .compatible = "mediatek,mt8195-vdo1-rdma", },
  

•   {},
  

+}; +MODULE_DEVICE_TABLE(of, mtk_mdp_rdma_driver_dt_match);

+struct platform_driver mtk_mdp_rdma_driver = {

•   .probe = mtk_mdp_rdma_probe,
  

•   .remove = mtk_mdp_rdma_remove,
  

•   .driver = {
  

•           .name = "mediatek-mdp-rdma",
  

•           .owner = THIS_MODULE,
  

•           .of_match_table = mtk_mdp_rdma_driver_dt_match,
  

•   },
  

+}; +module_platform_driver(mtk_mdp_rdma_driver); diff --git a/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h new file mode 100644 index 000000000000..868e8ca40de3 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_mdp_rdma.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#ifndef __MTK_MDP_RDMA_H__ +#define __MTK_MDP_RDMA_H__

+struct mtk_mdp_rdma_cfg {

•   unsigned int pitch;
  

•   unsigned int addr0;
  

•   unsigned int width;
  

•   unsigned int height;
  

•   unsigned int x_left;
  

•   unsigned int y_top;
  

•   int fmt;
  

+};

+#endif // __MTK_MDP_RDMA_H__

2.18.0

Hi, Nancy:

Nancy.Lin nancy.lin@mediatek.com 於 2021年10月4日 週一 下午2:21寫道：

Add merge new API.

1. Vdosys1 merge1~merge4 support HW mute function, so add unmute API.
2. Add merge new advance config API. The original merge API is mtk_ddp_comp_funcs function prototype. The API interface parameters cannot be modified, so add a new config API for extension.
3. Add merge enable/disable API for cmdq support. The ovl_adaptor merges are configured with each drm plane update. Need to enable/disable merge with cmdq making sure all the settings taken effect in the same vblank.

Separate this patch into three patches.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++ drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86 ++++++++++++++++++++--- 2 files changed, 82 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index b3a372cab0bd..2446ad0a4977 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev, unsigned int width, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_merge_start(struct device *dev); void mtk_merge_stop(struct device *dev); +void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,

•                         unsigned int h, unsigned int vrefresh, unsigned int bpc,
  

•                         struct cmdq_pkt *cmdq_pkt);
  

+void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt); +void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt); +void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt);

void mtk_ovl_bgclr_in_on(struct device *dev); void mtk_ovl_bgclr_in_off(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c index b05e1df79c3d..696bb948352b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c @@ -17,6 +17,7 @@ #define DISP_REG_MERGE_CTRL 0x000 #define MERGE_EN 1 #define DISP_REG_MERGE_CFG_0 0x010 +#define DISP_REG_MERGE_CFG_1 0x014 #define DISP_REG_MERGE_CFG_4 0x020 #define DISP_REG_MERGE_CFG_10 0x038 /* no swap */ @@ -25,9 +26,12 @@ #define DISP_REG_MERGE_CFG_12 0x040 #define CFG_10_10_1PI_2PO_BUF_MODE 6 #define CFG_10_10_2PI_2PO_BUF_MODE 8 +#define CFG_11_10_1PI_2PO_MERGE 18 #define FLD_CFG_MERGE_MODE GENMASK(4, 0) #define DISP_REG_MERGE_CFG_24 0x070 #define DISP_REG_MERGE_CFG_25 0x074 +#define DISP_REG_MERGE_CFG_26 0x078 +#define DISP_REG_MERGE_CFG_27 0x07c #define DISP_REG_MERGE_CFG_36 0x0a0 #define ULTRA_EN BIT(0) #define PREULTRA_EN BIT(4) @@ -54,26 +58,52 @@ #define FLD_PREULTRA_TH_LOW GENMASK(15, 0) #define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)

+#define DISP_REG_MERGE_MUTE_0 0xf00

struct mtk_disp_merge { void __iomem *regs; struct clk *clk; struct clk *async_clk; struct cmdq_client_reg cmdq_reg; bool fifo_en;

•   bool                            mute_support;
  

Align indent of members.

};

void mtk_merge_start(struct device *dev) +{

•   mtk_merge_enable(dev, NULL);
  

+}

+void mtk_merge_stop(struct device *dev) { struct mtk_disp_merge *priv = dev_get_drvdata(dev);

•   writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
  

•   mtk_merge_disable(dev, NULL);
  

}

-void mtk_merge_stop(struct device *dev) +void mtk_merge_enable(struct device *dev, struct cmdq_pkt *cmdq_pkt)

The difference of mtk_merge_enable() and mtk_merge_start() is cmdq support, but the naming make them so different. So I would like this function name to be mtk_merge_start_cmdq().

+{

•   struct mtk_disp_merge *priv = dev_get_drvdata(dev);
  

•   mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
  

•                 DISP_REG_MERGE_CTRL);
  

+}

+void mtk_merge_disable(struct device *dev, struct cmdq_pkt *cmdq_pkt)

Ditto.

{ struct mtk_disp_merge *priv = dev_get_drvdata(dev);

•   writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
  

•   mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
  

•                 DISP_REG_MERGE_CTRL);
  

+}

+void mtk_merge_unmute(struct device *dev, struct cmdq_pkt *cmdq_pkt)

I'm not sure whether it's worth to have this function. It seems that mtk_merge_enable() imply mtk_merge_unmute(). So I would like to move this function into mtk_merge_enable(). And I would like to mute in mtk_merge_disable() to let register be restored.

Regards, Chun-Kuang.

+{

•   struct mtk_disp_merge *priv = dev_get_drvdata(dev);
  

•   if (priv->mute_support)
  

•           mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
  

•                         DISP_REG_MERGE_MUTE_0);
  

}

static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv, @@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv, void mtk_merge_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{

•   mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc, cmdq_pkt);
  

+}

+void mtk_merge_advance_config(struct device *dev, unsigned int l_w, unsigned int r_w,

•                         unsigned int h, unsigned int vrefresh, unsigned int bpc,
  

•                         struct cmdq_pkt *cmdq_pkt)
  

{ struct mtk_disp_merge *priv = dev_get_drvdata(dev); unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;

•   if (!h || !w) {
  

•           dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
  

•   if (!h || !l_w) {
  

•           dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, l_w, h);
            return;
    }
  
  

@@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev, unsigned int w, mode = CFG_10_10_2PI_2PO_BUF_MODE; }

•   mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
  

•   if (r_w)
  

•           mode = CFG_11_10_1PI_2PO_MERGE;
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
                  DISP_REG_MERGE_CFG_0);
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
  

•                 DISP_REG_MERGE_CFG_1);
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv->cmdq_reg, priv->regs,
                  DISP_REG_MERGE_CFG_4);
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
  

•   /*
  

•    * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
  

•    * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
  

•    * If r_w > 0, the merge is in merge mode (input0 and input1 merge together),
  

•    * the input0 goes to SRAM0, and input1 goes to SRAM1.
  

•    * If r_w = 0, the merge is in buffer mode, the input goes through SRAM0 and
  

•    * then to SRAM1. Both SRAM0 and SRAM1 are set to the same size.
  

•    */
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
                  DISP_REG_MERGE_CFG_24);
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
  

•                 DISP_REG_MERGE_CFG_25);
  

•   if (r_w)
  

•           mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
  

•                         DISP_REG_MERGE_CFG_25);
  

•   else
  

•           mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
  

•                         DISP_REG_MERGE_CFG_25);
  

•   /*
  

•    * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only used in LR merge.
  

•    * Only take effect when the merge is setting to merge mode.
  

•    */
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg, priv->regs,
  

•                 DISP_REG_MERGE_CFG_26);
  

•   mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg, priv->regs,
  

•                 DISP_REG_MERGE_CFG_27);
  

•   mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
                       DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
    mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
  

@@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct platform_device *pdev) priv->fifo_en = of_property_read_bool(dev->of_node, "mediatek,merge-fifo-en");

•   priv->mute_support = of_property_read_bool(dev->of_node,
  

•                                              "mediatek,merge-mute");
    platform_set_drvdata(pdev, priv);
  
    ret = component_add(dev, &mtk_disp_merge_component_ops);
  

-- 2.18.0

Hi Chun-Kuang,

Thanks for the review.

On Thu, 2021-10-21 at 23:44 +0800, Chun-Kuang Hu wrote:

Hi, Nancy:

Nancy.Lin nancy.lin@mediatek.com 於 2021年10月4日 週一 下午2:22寫道：

...

ETHDR is a part of ovl_adaptor. ETHDR is designed for HDR video and graphics conversion in the external display path. It handles multiple HDR input types and performs tone mapping, color space/color format conversion, and then combine different layers, output the required HDR or SDR signal to the subsequent display path.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_ethdr.c | 403 +++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ethdr.h | 25 ++ 3 files changed, 429 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.c create mode 100644 drivers/gpu/drm/mediatek/mtk_ethdr.h

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index 6e604a933ed0..fb158a1e7f06 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -14,6 +14,7 @@ mediatek-drm-y := mtk_disp_aal.o \ mtk_drm_plane.o \ mtk_dsi.o \ mtk_dpi.o \

•             mtk_ethdr.o \
              mtk_mdp_rdma.o
  
  

obj-$(CONFIG_DRM_MEDIATEK) += mediatek-drm.o diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c new file mode 100644 index 000000000000..99e5a95aebed --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c @@ -0,0 +1,403 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#include <drm/drm_fourcc.h> +#include <linux/clk.h> +#include <linux/reset.h> +#include <linux/component.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h> +#include <linux/soc/mediatek/mtk-mmsys.h>

+#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" +#include "mtk_drm_drv.h" +#include "mtk_ethdr.h"

+#define MIX_INTEN 0x4

•   #define MIX_FME_CPL_INTEN       BIT(1)
  

Align the indent with mdp rdma driver.

OK.

...

+#define MIX_INTSTA 0x8 +#define MIX_EN 0xc +#define MIX_RST 0x14 +#define MIX_ROI_SIZE 0x18 +#define MIX_DATAPATH_CON 0x1c

•   #define OUTPUT_NO_RND   BIT(3)
  

•   #define SOURCE_RGB_SEL  BIT(7)
  

•   #define BACKGROUND_RELAY        (4 << 9)
  

+#define MIX_ROI_BGCLR 0x20

•   #define BGCLR_BLACK     0xff000000
  

+#define MIX_SRC_CON 0x24

•   #define MIX_SRC_L0_EN   BIT(0)
  

+#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))

•   #define NON_PREMULTI_SOURCE (2 << 12)
  

+#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n)) +#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n)) +#define MIX_FUNC_DCM0 0x120 +#define MIX_FUNC_DCM1 0x124

•   #define MIX_FUNC_DCM_ENABLE 0xffffffff
  

+#define HDR_VDO_FE_0804_HDR_DM_FE 0x804

•   #define HDR_VDO_FE_0804_BYPASS_ALL      0xfd
  

+#define HDR_GFX_FE_0204_GFX_HDR_FE 0x204

•   #define HDR_GFX_FE_0204_BYPASS_ALL      0xfd
  

+#define HDR_VDO_BE_0204_VDO_DM_BE 0x204

•   #define HDR_VDO_BE_0204_BYPASS_ALL      0x7e
  

+#define MIXER_INx_MODE_BYPASS 0

MIXER_INX_MODE_BYPASS

OK.

...

+#define MIXER_INx_MODE_EVEN_EXTEND 1 +#define MIXER_INx_MODE_ODD_EXTEND 2 +#define DEFAULT_9BIT_ALPHA 0x100 +#define MIXER_ALPHA_AEN BIT(8) +#define MIXER_ALPHA 0xff +#define ETHDR_CLK_NUM 13

+enum mtk_ethdr_comp_id {

•   ETHDR_MIXER,
  

•   ETHDR_VDO_FE0,
  

•   ETHDR_VDO_FE1,
  

•   ETHDR_GFX_FE0,
  

•   ETHDR_GFX_FE1,
  

•   ETHDR_VDO_BE,
  

•   ETHDR_ADL_DS,
  

•   ETHDR_ID_MAX
  

+};

+struct mtk_ethdr_comp {

•   struct device *dev;
  

•   void __iomem *regs;
  

•   struct cmdq_client_reg cmdq_base;
  

+};

+struct mtk_ethdr {

•   struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
  

•   struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
  

•   struct device *mmsys_dev;
  

•   spinlock_t lock; /* protects vblank_cb and vblank_cb_data
  

*/

•   void (*vblank_cb)(void *data);
  

•   void *vblank_cb_data;
  

•   int irq;
  

+};

+static const char * const ethdr_comp_str[] = {

•   "ETHDR_MIXER",
  

•   "ETHDR_VDO_FE0",
  

•   "ETHDR_VDO_FE1",
  

•   "ETHDR_GFX_FE0",
  

•   "ETHDR_GFX_FE1",
  

•   "ETHDR_VDO_BE",
  

•   "ETHDR_ADL_DS",
  

•   "ETHDR_ID_MAX"
  

+};

+static const char * const ethdr_clk_str[] = {

•   "ethdr_top",
  

•   "mixer",
  

•   "vdo_fe0",
  

•   "vdo_fe1",
  

•   "gfx_fe0",
  

•   "gfx_fe1",
  

•   "vdo_be",
  

•   "adl_ds",
  

•   "vdo_fe0_async",
  

•   "vdo_fe1_async",
  

•   "gfx_fe0_async",
  

•   "gfx_fe1_async",
  

•   "vdo_be_async",
  

+};

+void mtk_ethdr_enable_vblank(struct device *dev,

•                        void (*vblank_cb)(void *),
  

•                        void *vblank_cb_data)
  

+{

•   struct mtk_ethdr *priv = dev_get_drvdata(dev);
  

•   unsigned long flags;
  

•   spin_lock_irqsave(&priv->lock, flags);
  

•   priv->vblank_cb = vblank_cb;
  

•   priv->vblank_cb_data = vblank_cb_data;
  

•   spin_unlock_irqrestore(&priv->lock, flags);
  

•   writel(MIX_FME_CPL_INTEN, priv-
  

...

ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);

+}

+void mtk_ethdr_disable_vblank(struct device *dev) +{

•   struct mtk_ethdr *priv = dev_get_drvdata(dev);
  

•   unsigned long flags;
  

•   spin_lock_irqsave(&priv->lock, flags);
  

•   priv->vblank_cb = NULL;
  

•   priv->vblank_cb_data = NULL;
  

•   spin_unlock_irqrestore(&priv->lock, flags);
  

•   writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
  

MIX_INTEN); +}

+static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id) +{

•   struct mtk_ethdr *priv = dev_id;
  

•   unsigned long flags;
  

•   writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs +
  

MIX_INTSTA);

•   spin_lock_irqsave(&priv->lock, flags);
  

•   if (!priv->vblank_cb) {
  

•           spin_unlock_irqrestore(&priv->lock, flags);
  

•           return IRQ_NONE;
  

•   }
  

•   priv->vblank_cb(priv->vblank_cb_data);
  

•   spin_unlock_irqrestore(&priv->lock, flags);
  

•   return IRQ_HANDLED;
  

+}

+void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,

•                       struct mtk_plane_state *state,
  

•                       struct cmdq_pkt *cmdq_pkt)
  

+{

•   struct mtk_ethdr *priv = dev_get_drvdata(dev);
  

•   struct mtk_ethdr_comp *mixer = &priv-
  

...

ethdr_comp[ETHDR_MIXER];

•   struct mtk_plane_pending_state *pending = &state->pending;
  

•   unsigned int offset = (pending->x & 1) << 31 | pending->y
  

<< 16 | pending->x;

•   unsigned int mixer_pad_mode = MIXER_INx_MODE_BYPASS;
  

•   unsigned int alpha_con = 0;
  

•   unsigned int fmt = 0;
  

fmt is useless, so remove.

OK.

...

•   dev_dbg(dev, "%s+ idx:%d", __func__, idx);
  

•   if (idx >= 4)
  

•           return;
  

•   if (!pending->enable) {
  

•           mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base,
  

mixer->regs, MIX_L_SRC_SIZE(idx));

•           mtk_mmsys_ddp_config(priv->mmsys_dev,
  

MMSYS_CONFIG_MIXER_IN_MODE,

•                                idx + 1,
  

MIXER_INx_MODE_BYPASS, cmdq_pkt);

•           mtk_mmsys_ddp_config(priv->mmsys_dev,
  

MMSYS_CONFIG_MIXER_IN_BIWIDTH,

•                                idx + 1, 0, cmdq_pkt);
  

•           return;
  

•   }
  

•   if (pending->x % 2)
  

•           mixer_pad_mode = MIXER_INx_MODE_EVEN_EXTEND;
  

•   mtk_mmsys_ddp_config(priv->mmsys_dev,
  

MMSYS_CONFIG_MIXER_IN_MODE,

•                        idx + 1, mixer_pad_mode, cmdq_pkt);
  

Drop mixer_pad_mode, and

mtk_mmsys_ddp_config(priv->mmsys_dev, MMSYS_CONFIG_MIXER_IN_MODE, idx

• 1, pending->x & 1 ? MIXER_INx_MODE_EVEN_EXTEND :

MIXER_INx_MODE_BYPASS, cmdq_pkt);

OK.

Regards, Chun-Kuang.

Regards, Nancy

...

•   mtk_mmsys_ddp_config(priv->mmsys_dev,
  

MMSYS_CONFIG_MIXER_IN_BIWIDTH,

•                        idx + 1, pending->width / 2 - 1,
  

cmdq_pkt);

•   if (state->base.fb && state->base.fb->format->has_alpha) {
  

•           alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
  

•           mtk_mmsys_ddp_config(priv->mmsys_dev,
  

MMSYS_CONFIG_HDR_ALPHA_SEL,

•                                idx + 1, 0, cmdq_pkt);
  

•   } else {
  

•           mtk_mmsys_ddp_config(priv->mmsys_dev,
  

MMSYS_CONFIG_HDR_ALPHA_SEL,

•                                idx + 1, 1, cmdq_pkt);
  

•   }
  

•   mtk_mmsys_ddp_config(priv->mmsys_dev,
  

MMSYS_CONFIG_MIXER_IN_ALPHA_ODD, idx + 1,

•                        DEFAULT_9BIT_ALPHA, cmdq_pkt);
  

•   mtk_mmsys_ddp_config(priv->mmsys_dev,
  

MMSYS_CONFIG_MIXER_IN_ALPHA_EVEN, idx + 1,

•                        DEFAULT_9BIT_ALPHA, cmdq_pkt);
  

•   mtk_ddp_write(cmdq_pkt, pending->height << 16 | pending-
  

...

width, &mixer->cmdq_base,

•                 mixer->regs, MIX_L_SRC_SIZE(idx));
  

•   mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer-
  

...

regs, MIX_L_SRC_OFFSET(idx));

•   mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base,
  

mixer->regs, MIX_L_SRC_CON(idx),

•                      0x1ff);
  

•   mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base,
  

mixer->regs, MIX_SRC_CON,

•                      BIT(idx));
  

+}

Add ovl_adaptor driver for MT8195. Ovl_adaptor is an encapsulated module and designed for simplified DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and an ETHDR. Two RDMAs merge into one layer, so this module support 4 layers.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 + .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 4 files changed, 516 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index fb158a1e7f06..3abd27d7c91d 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \ mtk_disp_gamma.o \ mtk_disp_merge.o \ mtk_disp_ovl.o \

•   mtk_disp_ovl_adaptor.o \
  

  mtk_disp_rdma.o \ mtk_drm_crtc.o \ mtk_drm_ddp_comp.o \

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 2446ad0a4977..6a4f4c42aedb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev, void *vblank_cb_data); void mtk_rdma_disable_vblank(struct device *dev);

+int mtk_ovl_adaptor_clk_enable(struct device *dev); +void mtk_ovl_adaptor_clk_disable(struct device *dev); +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,

• 	    unsigned int h, unsigned int vrefresh,
  

• 	    unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
  

+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,

• 		  struct mtk_plane_state *state,
  

• 		  struct cmdq_pkt *cmdq_pkt);
  

+void mtk_ovl_adaptor_enable_vblank(struct device *dev,

• 		   void (*vblank_cb)(void *),
  

• 		   void *vblank_cb_data);
  

+void mtk_ovl_adaptor_disable_vblank(struct device *dev); +void mtk_ovl_adaptor_start(struct device *dev); +void mtk_ovl_adaptor_stop(struct device *dev); +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);

• int mtk_mdp_rdma_clk_enable(struct device *dev); void mtk_mdp_rdma_clk_disable(struct device *dev); void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt);

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c new file mode 100644 index 000000000000..bfb5a9d29c26 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#include <drm/drm_fourcc.h> +#include <drm/drm_of.h> +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/reset.h> +#include <linux/soc/mediatek/mtk-mmsys.h> +#include <linux/soc/mediatek/mtk-cmdq.h>

+#include "mtk_drm_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" +#include "mtk_disp_drv.h" +#include "mtk_ethdr.h"

+#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920 +#define MTK_OVL_ADAPTOR_LAYER_NUM 4

+enum mtk_ovl_adaptor_comp_type {

• OVL_ADAPTOR_TYPE_RDMA = 0,
• OVL_ADAPTOR_TYPE_MERGE,
• OVL_ADAPTOR_TYPE_ETHDR,
• OVL_ADAPTOR_TYPE_NUM,

+};

+enum mtk_ovl_adaptor_comp_id {

• OVL_ADAPTOR_MDP_RDMA0,
• OVL_ADAPTOR_MDP_RDMA1,
• OVL_ADAPTOR_MDP_RDMA2,
• OVL_ADAPTOR_MDP_RDMA3,
• OVL_ADAPTOR_MDP_RDMA4,
• OVL_ADAPTOR_MDP_RDMA5,
• OVL_ADAPTOR_MDP_RDMA6,
• OVL_ADAPTOR_MDP_RDMA7,
• OVL_ADAPTOR_MERGE0,
• OVL_ADAPTOR_MERGE1,
• OVL_ADAPTOR_MERGE2,
• OVL_ADAPTOR_MERGE3,
• OVL_ADAPTOR_ETHDR0,
• OVL_ADAPTOR_ID_MAX

+};

+struct ovl_adaptor_comp_match {

• enum mtk_ovl_adaptor_comp_type type;
• int alias_id;

+};

+struct mtk_disp_ovl_adaptor {

• struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
• struct device *mmsys_dev;

+};

+static const char * const ovl_adaptor_comp_str[] = {

• "OVL_ADAPTOR_MDP_RDMA0",
• "OVL_ADAPTOR_MDP_RDMA1",
• "OVL_ADAPTOR_MDP_RDMA2",
• "OVL_ADAPTOR_MDP_RDMA3",
• "OVL_ADAPTOR_MDP_RDMA4",
• "OVL_ADAPTOR_MDP_RDMA5",
• "OVL_ADAPTOR_MDP_RDMA6",
• "OVL_ADAPTOR_MDP_RDMA7",
• "OVL_ADAPTOR_MERGE0",
• "OVL_ADAPTOR_MERGE1",
• "OVL_ADAPTOR_MERGE2",
• "OVL_ADAPTOR_MERGE3",
• "OVL_ADAPTOR_ETHDR",
• "OVL_ADAPTOR_ID_MAX"

+};

+static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {

• [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
• [OVL_ADAPTOR_TYPE_MERGE] = "merge",
• [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",

+};

+static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {

• [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_RDMA, 0 },
• [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_RDMA, 1 },
• [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_RDMA, 2 },
• [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_RDMA, 3 },
• [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_RDMA, 4 },
• [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_RDMA, 5 },
• [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_RDMA, 6 },
• [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_RDMA, 7 },
• [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, 1 },
• [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, 2 },
• [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, 3 },
• [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, 4 },
• [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, 0 },

+};

nit: can you please fix the indentation here?

+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,

• 		  struct mtk_plane_state *state,
  

• 		  struct cmdq_pkt *cmdq_pkt)
  

+{

• struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
• struct mtk_plane_pending_state *pending = &state->pending;
• struct mtk_mdp_rdma_cfg rdma_config = {0};
• struct device *rdma_l;
• struct device *rdma_r;
• struct device *merge;
• struct device *ethdr;
• const struct drm_format_info *fmt_info = drm_format_info(pending->format);
• bool use_dual_pipe = false;
• unsigned int l_w = 0;
• unsigned int r_w = 0;
• dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,

• pending->enable, pending->format);
  

• dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",

• pending->addr, (pending->pitch / fmt_info->cpp[0]),
  

• pending->x, pending->y, pending->width, pending->height);
  

• rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
• rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
• merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
• ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
• if (!pending->enable) {

• mtk_merge_disable(merge, cmdq_pkt);
  

• mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
  

• mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
  

• mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
  

• return;
  

• }
• /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
• pending->width = ALIGN_DOWN(pending->width, 2);
• if (pending->width > MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH)

• use_dual_pipe = true;
  

• if (use_dual_pipe) {

• l_w = (pending->width / 2) + ((pending->width / 2) % 2);
  

• r_w = pending->width - l_w;
  

• } else {

• l_w = pending->width;
  

• }
• mtk_merge_advance_config(merge, l_w, r_w, pending->height, 0, 0, cmdq_pkt);
• mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_WIDTH,

• 	     idx, pending->width / 2, cmdq_pkt);
  

• mtk_mmsys_ddp_config(ovl_adaptor->mmsys_dev, MMSYS_CONFIG_MERGE_ASYNC_HEIGHT,

• 	     idx, pending->height, cmdq_pkt);
  

• rdma_config.width = l_w;
• rdma_config.height = pending->height;
• rdma_config.addr0 = pending->addr;
• rdma_config.pitch = pending->pitch;
• rdma_config.fmt = pending->format;
• mtk_mdp_rdma_config(rdma_l, &rdma_config, cmdq_pkt);
• if (use_dual_pipe) {

• rdma_config.x_left = l_w;
  

• rdma_config.width = r_w;
  

• mtk_mdp_rdma_config(rdma_r, &rdma_config, cmdq_pkt);
  

• }
• mtk_merge_enable(merge, cmdq_pkt);
• mtk_merge_unmute(merge, cmdq_pkt);
• mtk_mdp_rdma_start(rdma_l, cmdq_pkt);
• if (use_dual_pipe)

• mtk_mdp_rdma_start(rdma_r, cmdq_pkt);
  

• else

• mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
  

• mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);

+}

+void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,

• 	    unsigned int h, unsigned int vrefresh,
  

• 	    unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
  

+{

• struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
• mtk_ethdr_config(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0], w, h,

• 	 vrefresh, bpc, cmdq_pkt);
  

+}

+void mtk_ovl_adaptor_start(struct device *dev) +{

• struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
• mtk_ethdr_start(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);

+}

+void mtk_ovl_adaptor_stop(struct device *dev) +{

• struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
• struct device *rdma_l;
• struct device *rdma_r;
• struct device *merge;
• u32 i;
• for (i = 0; i < MTK_OVL_ADAPTOR_LAYER_NUM; i++) {

• rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i];
  

• rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * i + 1];
  

• merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + i];
  

• mtk_mdp_rdma_stop(rdma_l, NULL);
  

• mtk_mdp_rdma_stop(rdma_r, NULL);
  

• mtk_merge_stop(merge);
  

• }
• mtk_ethdr_stop(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);

+}

+int mtk_ovl_adaptor_clk_enable(struct device *dev) +{

• struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
• struct device *comp;
• int ret;
• int i;
• for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {

• comp = ovl_adaptor->ovl_adaptor_comp[i];
  

• if (i < OVL_ADAPTOR_MERGE0)
  

• 	ret = mtk_mdp_rdma_clk_enable(comp);
  

• else if (i < OVL_ADAPTOR_ETHDR0)
  

• 	ret = mtk_merge_clk_enable(comp);
  

• else
  

• 	ret = mtk_ethdr_clk_enable(comp);
  

• if (ret) {
  

• 	dev_err(dev,
  

• 		"Failed to enable clock %d, err %d-%s\n",
  

• 		i, ret, ovl_adaptor_comp_str[i]);
  

• 	goto clk_err;
  

• }
  

• }
• return ret;

+clk_err:

• while (--i >= 0) {

• comp = ovl_adaptor->ovl_adaptor_comp[i];
  

• if (i < OVL_ADAPTOR_MERGE0)
  

• 	mtk_mdp_rdma_clk_disable(comp);
  

• else if (i < OVL_ADAPTOR_ETHDR0)
  

• 	mtk_merge_clk_disable(comp);
  

• else
  

• 	mtk_ethdr_clk_disable(comp);
  

• }
• return ret;

+}

+void mtk_ovl_adaptor_clk_disable(struct device *dev) +{

• struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
• struct device *comp;
• int i;
• for (i = OVL_ADAPTOR_MDP_RDMA0; i < OVL_ADAPTOR_ID_MAX; i++) {

• comp = ovl_adaptor->ovl_adaptor_comp[i];
  

• if (i < OVL_ADAPTOR_MERGE0)
  

• 	mtk_mdp_rdma_clk_disable(comp);
  

• else if (i < OVL_ADAPTOR_ETHDR0)
  

• 	mtk_merge_clk_disable(comp);
  

• else
  

• 	mtk_ethdr_clk_disable(comp);
  

• }

+}

+unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev) +{

• return MTK_OVL_ADAPTOR_LAYER_NUM;

+}

+void mtk_ovl_adaptor_enable_vblank(struct device *dev, void (*vblank_cb)(void *),

• 		   void *vblank_cb_data)
  

+{

• struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
• mtk_ethdr_enable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0],

• 		vblank_cb, vblank_cb_data);
  

+}

+void mtk_ovl_adaptor_disable_vblank(struct device *dev) +{

• struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
• mtk_ethdr_disable_vblank(ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0]);

+}

+static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,

• 		   enum mtk_ovl_adaptor_comp_type type)
  

+{

• int alias_id = of_alias_get_id(node, private_comp_stem[type]);
• int ret;
• int i;
• for (i = 0; i < ARRAY_SIZE(comp_matches); i++)

• if (comp_matches[i].type == type &&
  

•     comp_matches[i].alias_id == alias_id)
  

• 	return i;
  

• dev_err(dev, "Failed to get id. type: %d, alias: %d\n", type, alias_id);
• return -EINVAL;

+}

+static const struct of_device_id mtk_ovl_adaptor_comp_dt_ids[] = {

• {

• .compatible = "mediatek,mt8195-vdo1-rdma",
  

• .data = (void *)OVL_ADAPTOR_TYPE_RDMA,
  

• }, {

• .compatible = "mediatek,mt8195-disp-merge",
  

• .data = (void *)OVL_ADAPTOR_TYPE_MERGE,
  

• }, {

• .compatible = "mediatek,mt8195-disp-ethdr",
  

• .data = (void *)OVL_ADAPTOR_TYPE_ETHDR,
  

• },
• {},

+};

+static int compare_of(struct device *dev, void *data) +{

• return dev->of_node == data;

+}

+static int ovl_adaptor_comp_init(struct device *dev, struct component_match **match) +{

• struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
• struct device_node *node, *parent;
• struct platform_device *comp_pdev;
• int i, ret;
• parent = dev->parent->parent->of_node->parent;
• for_each_child_of_node(parent, node) {

• const struct of_device_id *of_id;
  

• enum mtk_ovl_adaptor_comp_type type;
  

• int id;
  

• of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
  

• if (!of_id)
  

• 	continue;
  

• if (!of_device_is_available(node)) {
  

• 	dev_info(dev, "Skipping disabled component %pOF\n",
  

• 		 node);
  

This looks like being a debugging print, use dev_dbg please.

• 	continue;
  

• }
  

• type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
  

• id = ovl_adaptor_comp_get_id(dev, node, type);
  

• if (id < 0) {
  

• 	dev_warn(dev, "Skipping unknown component %pOF\n",
  

• 		 node);
  

• 	continue;
  

• }
  

• comp_pdev = of_find_device_by_node(node);
  

• if (!comp_pdev) {
  

• 	dev_warn(dev, "can't find platform device of node:%s\n",
  

• 		 node->name);
  

• 	return -ENODEV;
  

• }
  

• priv->ovl_adaptor_comp[id] = &comp_pdev->dev;
  

• drm_of_component_match_add(dev, match, compare_of, node);
  

• dev_info(dev, "Adding component match for %pOF\n", node);
  

...and this is another debugging print, imo.

• }
• return 0;

+}

+static int mtk_disp_ovl_adaptor_comp_bind(struct device *dev, struct device *master,

• 			  void *data)
  

+{

• return 0;

+}

+static void mtk_disp_ovl_adaptor_comp_unbind(struct device *dev, struct device *master,

• 			     void *data)
  

+{ +}

+static const struct component_ops mtk_disp_ovl_adaptor_comp_ops = {

• .bind = mtk_disp_ovl_adaptor_comp_bind,
• .unbind = mtk_disp_ovl_adaptor_comp_unbind,

+};

+static int mtk_disp_ovl_adaptor_master_bind(struct device *dev) +{

• struct mtk_disp_ovl_adaptor *priv = dev_get_drvdata(dev);
• dev_info(dev, "%s-%d", __func__, __LINE__);

Printing the line number here isn't giving any valuable information, as this function is almost a one-liner... plus, this is a debug print and, as such, you should either use dev_dbg instead or simply remove it: if anything needs debugging of this part, you'll probably want to use ftrace anyway, so I don't really see the need of having this print in place.

• component_bind_all(dev, priv->mmsys_dev);
• return 0;

+}

+static void mtk_disp_ovl_adaptor_master_unbind(struct device *dev) +{ +}

+static const struct component_master_ops mtk_disp_ovl_adaptor_master_ops = {

• .bind = mtk_disp_ovl_adaptor_master_bind,
• .unbind = mtk_disp_ovl_adaptor_master_unbind,

+};

+static int mtk_disp_ovl_adaptor_check_comp(struct device *dev) +{

• struct device_node *node;
• for_each_child_of_node(dev->parent->parent->of_node->parent, node) {

• const struct of_device_id *of_id;
  

• struct platform_device *comp_pdev;
  

• enum mtk_ovl_adaptor_comp_type type;
  

• int id;
  

• of_id = of_match_node(mtk_ovl_adaptor_comp_dt_ids, node);
  

• if (!of_id)
  

• 	continue;
  

• if (!of_device_is_available(node))
  

• 	continue;
  

• type = (enum mtk_ovl_adaptor_comp_type)of_id->data;
  

• id = ovl_adaptor_comp_get_id(dev, node, type);
  

• if (id < 0)
  

• 	continue;
  

• comp_pdev = of_find_device_by_node(node);
  

• if (!comp_pdev)
  

• 	return -EPROBE_DEFER;
  

• if (!platform_get_drvdata(comp_pdev))
  

• 	return -EPROBE_DEFER;
  

• }
• return 0;

+}

+static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev) +{

• struct mtk_disp_ovl_adaptor *priv;
• struct device *dev = &pdev->dev;
• struct component_match *match = NULL;
• int ret;
• dev_info(dev, "%s+\n", __func__);

If you want to know when you're hitting a function, you should use ftrace instead of a print. Please remove this message.

• ret = mtk_disp_ovl_adaptor_check_comp(dev);
• if (ret < 0)

• return ret;
  

• priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
• if (!priv)

• return -ENOMEM;
  

• priv->mmsys_dev = pdev->dev.platform_data;
• platform_set_drvdata(pdev, priv);
• ret = ovl_adaptor_comp_init(dev, &match);
• if (ret) {

• dev_notice(dev, "ovl_adaptor comp init fail\n");
  

• return ret;
  

• }
• component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, match);
• pm_runtime_enable(dev);
• ret = component_add(dev, &mtk_disp_ovl_adaptor_comp_ops);
• if (ret != 0) {

• pm_runtime_disable(dev);
  

• dev_err(dev, "Failed to add component: %d\n", ret);
  

• }
• dev_info(dev, "%s-\n", __func__);

Also remove this one.

• return ret;

+}

+static int mtk_disp_ovl_adaptor_remove(struct platform_device *pdev) +{

• component_del(&pdev->dev, &mtk_disp_ovl_adaptor_comp_ops);
• pm_runtime_disable(&pdev->dev);
• return 0;

+}

+struct platform_driver mtk_disp_ovl_adaptor_driver = {

• .probe = mtk_disp_ovl_adaptor_probe,
• .remove = mtk_disp_ovl_adaptor_remove,
• .driver = {

• 	.name = "mediatek-disp-ovl-adaptor",
  

• 	.owner = THIS_MODULE,
  

• },
  

Please fix indentation: .driver = { ....... },

Regards, - Angelo

Hi, Nancy:

Nancy.Lin nancy.lin@mediatek.com 於 2021年10月4日 週一 下午2:21寫道：

Add ovl_adaptor driver for MT8195. Ovl_adaptor is an encapsulated module and designed for simplified DRM control flow. This module is composed of 8 RDMAs, 4 MERGEs and an ETHDR. Two RDMAs merge into one layer, so this module support 4 layers.

Signed-off-by: Nancy.Lin nancy.lin@mediatek.com

drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_disp_drv.h | 16 + .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 498 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 + 4 files changed, 516 insertions(+) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile index fb158a1e7f06..3abd27d7c91d 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -6,6 +6,7 @@ mediatek-drm-y := mtk_disp_aal.o \ mtk_disp_gamma.o \ mtk_disp_merge.o \ mtk_disp_ovl.o \

•             mtk_disp_ovl_adaptor.o \
              mtk_disp_rdma.o \
              mtk_drm_crtc.o \
              mtk_drm_ddp_comp.o \
  

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 2446ad0a4977..6a4f4c42aedb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -113,6 +113,22 @@ void mtk_rdma_enable_vblank(struct device *dev, void *vblank_cb_data); void mtk_rdma_disable_vblank(struct device *dev);

+int mtk_ovl_adaptor_clk_enable(struct device *dev); +void mtk_ovl_adaptor_clk_disable(struct device *dev); +void mtk_ovl_adaptor_config(struct device *dev, unsigned int w,

•                       unsigned int h, unsigned int vrefresh,
  

•                       unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
  

+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,

•                             struct mtk_plane_state *state,
  

•                             struct cmdq_pkt *cmdq_pkt);
  

+void mtk_ovl_adaptor_enable_vblank(struct device *dev,

•                              void (*vblank_cb)(void *),
  

•                              void *vblank_cb_data);
  

+void mtk_ovl_adaptor_disable_vblank(struct device *dev); +void mtk_ovl_adaptor_start(struct device *dev); +void mtk_ovl_adaptor_stop(struct device *dev); +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev);

int mtk_mdp_rdma_clk_enable(struct device *dev); void mtk_mdp_rdma_clk_disable(struct device *dev); void mtk_mdp_rdma_start(struct device *dev, struct cmdq_pkt *cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c new file mode 100644 index 000000000000..bfb5a9d29c26 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0-only +/*

• • Copyright (c) 2021 MediaTek Inc.
• */

+#include <drm/drm_fourcc.h> +#include <drm/drm_of.h> +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/reset.h> +#include <linux/soc/mediatek/mtk-mmsys.h> +#include <linux/soc/mediatek/mtk-cmdq.h>

+#include "mtk_drm_drv.h" +#include "mtk_drm_crtc.h" +#include "mtk_drm_ddp_comp.h" +#include "mtk_disp_drv.h"

Alphabetic order.

+#include "mtk_ethdr.h"

+#define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920 +#define MTK_OVL_ADAPTOR_LAYER_NUM 4

+enum mtk_ovl_adaptor_comp_type {

•   OVL_ADAPTOR_TYPE_RDMA = 0,
  

•   OVL_ADAPTOR_TYPE_MERGE,
  

•   OVL_ADAPTOR_TYPE_ETHDR,
  

•   OVL_ADAPTOR_TYPE_NUM,
  

+};

+enum mtk_ovl_adaptor_comp_id {

•   OVL_ADAPTOR_MDP_RDMA0,
  

•   OVL_ADAPTOR_MDP_RDMA1,
  

•   OVL_ADAPTOR_MDP_RDMA2,
  

•   OVL_ADAPTOR_MDP_RDMA3,
  

•   OVL_ADAPTOR_MDP_RDMA4,
  

•   OVL_ADAPTOR_MDP_RDMA5,
  

•   OVL_ADAPTOR_MDP_RDMA6,
  

•   OVL_ADAPTOR_MDP_RDMA7,
  

•   OVL_ADAPTOR_MERGE0,
  

•   OVL_ADAPTOR_MERGE1,
  

•   OVL_ADAPTOR_MERGE2,
  

•   OVL_ADAPTOR_MERGE3,
  

•   OVL_ADAPTOR_ETHDR0,
  

•   OVL_ADAPTOR_ID_MAX
  

+};

+struct ovl_adaptor_comp_match {

•   enum mtk_ovl_adaptor_comp_type type;
  

•   int alias_id;
  

+};

+struct mtk_disp_ovl_adaptor {

•   struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX];
  

•   struct device *mmsys_dev;
  

+};

+static const char * const ovl_adaptor_comp_str[] = {

•   "OVL_ADAPTOR_MDP_RDMA0",
  

•   "OVL_ADAPTOR_MDP_RDMA1",
  

•   "OVL_ADAPTOR_MDP_RDMA2",
  

•   "OVL_ADAPTOR_MDP_RDMA3",
  

•   "OVL_ADAPTOR_MDP_RDMA4",
  

•   "OVL_ADAPTOR_MDP_RDMA5",
  

•   "OVL_ADAPTOR_MDP_RDMA6",
  

•   "OVL_ADAPTOR_MDP_RDMA7",
  

•   "OVL_ADAPTOR_MERGE0",
  

•   "OVL_ADAPTOR_MERGE1",
  

•   "OVL_ADAPTOR_MERGE2",
  

•   "OVL_ADAPTOR_MERGE3",
  

•   "OVL_ADAPTOR_ETHDR",
  

•   "OVL_ADAPTOR_ID_MAX"
  

+};

+static const char * const private_comp_stem[OVL_ADAPTOR_TYPE_NUM] = {

•   [OVL_ADAPTOR_TYPE_RDMA] = "vdo1_rdma",
  

•   [OVL_ADAPTOR_TYPE_MERGE] = "merge",
  

•   [OVL_ADAPTOR_TYPE_ETHDR] = "ethdr",
  

+};

+static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {

•   [OVL_ADAPTOR_MDP_RDMA0] =       { OVL_ADAPTOR_TYPE_RDMA, 0 },
  

•   [OVL_ADAPTOR_MDP_RDMA1] =       { OVL_ADAPTOR_TYPE_RDMA, 1 },
  

•   [OVL_ADAPTOR_MDP_RDMA2] =       { OVL_ADAPTOR_TYPE_RDMA, 2 },
  

•   [OVL_ADAPTOR_MDP_RDMA3] =       { OVL_ADAPTOR_TYPE_RDMA, 3 },
  

•   [OVL_ADAPTOR_MDP_RDMA4] =       { OVL_ADAPTOR_TYPE_RDMA, 4 },
  

•   [OVL_ADAPTOR_MDP_RDMA5] =       { OVL_ADAPTOR_TYPE_RDMA, 5 },
  

•   [OVL_ADAPTOR_MDP_RDMA6] =       { OVL_ADAPTOR_TYPE_RDMA, 6 },
  

•   [OVL_ADAPTOR_MDP_RDMA7] =       { OVL_ADAPTOR_TYPE_RDMA, 7 },
  

•   [OVL_ADAPTOR_MERGE0] =  { OVL_ADAPTOR_TYPE_MERGE, 1 },
  

•   [OVL_ADAPTOR_MERGE1] =  { OVL_ADAPTOR_TYPE_MERGE, 2 },
  

•   [OVL_ADAPTOR_MERGE2] =  { OVL_ADAPTOR_TYPE_MERGE, 3 },
  

•   [OVL_ADAPTOR_MERGE3] =  { OVL_ADAPTOR_TYPE_MERGE, 4 },
  

•   [OVL_ADAPTOR_ETHDR0] =  { OVL_ADAPTOR_TYPE_ETHDR, 0 },
  

+};

+void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,

•                             struct mtk_plane_state *state,
  

•                             struct cmdq_pkt *cmdq_pkt)
  

+{

•   struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev);
  

•   struct mtk_plane_pending_state *pending = &state->pending;
  

•   struct mtk_mdp_rdma_cfg rdma_config = {0};
  

•   struct device *rdma_l;
  

•   struct device *rdma_r;
  

•   struct device *merge;
  

•   struct device *ethdr;
  

•   const struct drm_format_info *fmt_info = drm_format_info(pending->format);
  

•   bool use_dual_pipe = false;
  

•   unsigned int l_w = 0;
  

•   unsigned int r_w = 0;
  

•   dev_dbg(dev, "%s+ idx:%d, enable:%d, fmt:0x%x\n", __func__, idx,
  

•           pending->enable, pending->format);
  

•   dev_dbg(dev, "addr 0x%lx, fb w:%d, {%d,%d,%d,%d}\n",
  

•           pending->addr, (pending->pitch / fmt_info->cpp[0]),
  

•           pending->x, pending->y, pending->width, pending->height);
  

•   rdma_l = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx];
  

•   rdma_r = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MDP_RDMA0 + 2 * idx + 1];
  

•   merge = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_MERGE0 + idx];
  

•   ethdr = ovl_adaptor->ovl_adaptor_comp[OVL_ADAPTOR_ETHDR0];
  

•   if (!pending->enable) {
  

•           mtk_merge_disable(merge, cmdq_pkt);
  

•           mtk_mdp_rdma_stop(rdma_l, cmdq_pkt);
  

•           mtk_mdp_rdma_stop(rdma_r, cmdq_pkt);
  

•           mtk_ethdr_layer_config(ethdr, idx, state, cmdq_pkt);
  

•           return;
  

•   }
  

•   /* ETHDR is in 1T2P domain, width needs to be 2 pixels align */
  

•   pending->width = ALIGN_DOWN(pending->width, 2);