The CMDQ (Command Queue) in MT8183 is used to help update all relevant display controller registers with critical time limation. This patch add cmdq interface in ddp_comp interface, let all ddp_comp interface can support cpu/cmdq function at the same time.
These patches also can fixup cursor moving is not smooth when heavy load in webgl.
This patch depends on ptach: add drm support for MT8183 (https://patchwork.kernel.org/cover/11121519/) support gce on mt8183 platform (https://patchwork.kernel.org/cover/11255147) drm/mediatek: Refactor plane init/check and support rotation (https://pw-emeril.freedesktop.org/series/69015/) drm/mediatek: Check return value of mtk_drm_ddp_comp_for_plane (https://lore.kernel.org/patchwork/patch/1154517/)
Changes since v3: - remove redundant code and variable
Changes since v2: - move some changes to another patch - disable layer in atomic_disable()
Changes since v1: - remove redundant code - merge the duplicate code - use async instead of cursor
Changes since v0: - remove redundant code - remove patch "drm/mediatek: fix atomic_state reference counting" After remove this patch, the issue we met before is gone. So I do not add any extra code to do something.
Bibby Hsieh (7): drm/mediatek: use DRM core's atomic commit helper drm/mediatek: handle events when enabling/disabling crtc drm/mediatek: update cursors by using async atomic update drm/mediatek: disable all the planes in atomic_disable drm/mediatek: remove unused external function drm/mediatek: support CMDQ interface in ddp component drm/mediatek: apply CMDQ control flow
drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 67 ++++---- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 43 ++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 165 ++++++++++++++++---- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 132 ++++++++++++---- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 47 +++--- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 86 +--------- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 - drivers/gpu/drm/mediatek/mtk_drm_plane.c | 47 ++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 + 11 files changed, 381 insertions(+), 224 deletions(-)
The DRM core atomic helper now supports asynchronous commits natively. The custom drm implementation isn't needed anymore, remove it.
Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 86 ++------------------------ drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 --- 2 files changed, 5 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 6588dc6dd5e3..16e5771d182e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -36,89 +36,14 @@ #define DRIVER_MAJOR 1 #define DRIVER_MINOR 0
-static void mtk_atomic_schedule(struct mtk_drm_private *private, - struct drm_atomic_state *state) -{ - private->commit.state = state; - schedule_work(&private->commit.work); -} - -static void mtk_atomic_complete(struct mtk_drm_private *private, - struct drm_atomic_state *state) -{ - struct drm_device *drm = private->drm; - - drm_atomic_helper_wait_for_fences(drm, state, false); - - /* - * Mediatek drm supports runtime PM, so plane registers cannot be - * written when their crtc is disabled. - * - * The comment for drm_atomic_helper_commit states: - * For drivers supporting runtime PM the recommended sequence is - * - * drm_atomic_helper_commit_modeset_disables(dev, state); - * drm_atomic_helper_commit_modeset_enables(dev, state); - * drm_atomic_helper_commit_planes(dev, state, - * DRM_PLANE_COMMIT_ACTIVE_ONLY); - * - * See the kerneldoc entries for these three functions for more details. - */ - drm_atomic_helper_commit_modeset_disables(drm, state); - drm_atomic_helper_commit_modeset_enables(drm, state); - drm_atomic_helper_commit_planes(drm, state, - DRM_PLANE_COMMIT_ACTIVE_ONLY); - - drm_atomic_helper_wait_for_vblanks(drm, state); - - drm_atomic_helper_cleanup_planes(drm, state); - drm_atomic_state_put(state); -} - -static void mtk_atomic_work(struct work_struct *work) -{ - struct mtk_drm_private *private = container_of(work, - struct mtk_drm_private, commit.work); - - mtk_atomic_complete(private, private->commit.state); -} - -static int mtk_atomic_commit(struct drm_device *drm, - struct drm_atomic_state *state, - bool async) -{ - struct mtk_drm_private *private = drm->dev_private; - int ret; - - ret = drm_atomic_helper_prepare_planes(drm, state); - if (ret) - return ret; - - mutex_lock(&private->commit.lock); - flush_work(&private->commit.work); - - ret = drm_atomic_helper_swap_state(state, true); - if (ret) { - mutex_unlock(&private->commit.lock); - drm_atomic_helper_cleanup_planes(drm, state); - return ret; - } - - drm_atomic_state_get(state); - if (async) - mtk_atomic_schedule(private, state); - else - mtk_atomic_complete(private, state); - - mutex_unlock(&private->commit.lock); - - return 0; -} +static const struct drm_mode_config_helper_funcs mtk_drm_mode_config_helpers = { + .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, +};
static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { .fb_create = mtk_drm_mode_fb_create, .atomic_check = drm_atomic_helper_check, - .atomic_commit = mtk_atomic_commit, + .atomic_commit = drm_atomic_helper_commit, };
static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { @@ -265,6 +190,7 @@ static int mtk_drm_kms_init(struct drm_device *drm) drm->mode_config.max_width = 4096; drm->mode_config.max_height = 4096; drm->mode_config.funcs = &mtk_drm_mode_config_funcs; + drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
ret = component_bind_all(drm->dev, drm); if (ret) @@ -540,8 +466,6 @@ static int mtk_drm_probe(struct platform_device *pdev) if (!private) return -ENOMEM;
- mutex_init(&private->commit.lock); - INIT_WORK(&private->commit.work, mtk_atomic_work); private->data = of_device_get_match_data(dev);
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h index b6a82728d563..9f4ce60174f6 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -46,13 +46,6 @@ struct mtk_drm_private { struct device_node *comp_node[DDP_COMPONENT_ID_MAX]; struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX]; const struct mtk_mmsys_driver_data *data; - - struct { - struct drm_atomic_state *state; - struct work_struct work; - struct mutex lock; - } commit; - struct drm_atomic_state *suspend_state;
bool dma_parms_allocated;
The driver currently handles vblank events only when updating planes on an already enabled CRTC. The atomic update API however allows requesting an event when enabling or disabling a CRTC. This currently leads to event objects being leaked in the kernel and to events not being sent out. Fix it.
Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index f5eeb0eebf76..4bc52346093d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -338,6 +338,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) { struct drm_device *drm = mtk_crtc->base.dev; + struct drm_crtc *crtc = &mtk_crtc->base; int i;
DRM_DEBUG_DRIVER("%s\n", __func__); @@ -364,6 +365,13 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) mtk_ddp_comp_unprepare(mtk_crtc->ddp_comp[i]);
pm_runtime_put(drm->dev); + + if (crtc->state->event && !crtc->state->active) { + spin_lock_irq(&crtc->dev->event_lock); + drm_crtc_send_vblank_event(crtc, crtc->state->event); + crtc->state->event = NULL; + spin_unlock_irq(&crtc->dev->event_lock); + } }
static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
Support to async updates of cursors by using the new atomic interface for that.
Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 98 +++++++++++++++++++----- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 + drivers/gpu/drm/mediatek/mtk_drm_plane.c | 47 ++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 + 4 files changed, 128 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 4bc52346093d..e887a6877bcd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -41,12 +41,16 @@ struct mtk_drm_crtc { struct drm_plane *planes; unsigned int layer_nr; bool pending_planes; + bool pending_async_planes;
void __iomem *config_regs; const struct mtk_mmsys_reg_data *mmsys_reg_data; struct mtk_disp_mutex *mutex; unsigned int ddp_comp_nr; struct mtk_ddp_comp **ddp_comp; + + /* lock for display hardware access */ + struct mutex hw_lock; };
struct mtk_crtc_state { @@ -415,6 +419,63 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) } mtk_crtc->pending_planes = false; } + + if (mtk_crtc->pending_async_planes) { + for (i = 0; i < mtk_crtc->layer_nr; i++) { + struct drm_plane *plane = &mtk_crtc->planes[i]; + struct mtk_plane_state *plane_state; + + plane_state = to_mtk_plane_state(plane->state); + + if (!plane_state->pending.async_config) + continue; + + comp = mtk_drm_ddp_comp_for_plane(crtc, plane, + &local_layer); + + if (comp) + mtk_ddp_comp_layer_config(comp, local_layer, + plane_state); + plane_state->pending.async_config = false; + } + mtk_crtc->pending_async_planes = false; + } +} + +static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) +{ + struct drm_crtc *crtc = &mtk_crtc->base; + struct mtk_drm_private *priv = crtc->dev->dev_private; + unsigned int pending_planes = 0, pending_async_planes = 0; + int i; + + mutex_lock(&mtk_crtc->hw_lock); + for (i = 0; i < mtk_crtc->layer_nr; i++) { + struct drm_plane *plane = &mtk_crtc->planes[i]; + struct mtk_plane_state *plane_state; + + plane_state = to_mtk_plane_state(plane->state); + if (plane_state->pending.dirty) { + plane_state->pending.config = true; + plane_state->pending.dirty = false; + pending_planes |= BIT(i); + } else if (plane_state->pending.async_dirty) { + plane_state->pending.async_config = true; + plane_state->pending.async_dirty = false; + pending_async_planes |= BIT(i); + } + } + if (pending_planes) + mtk_crtc->pending_planes = true; + if (pending_async_planes) + mtk_crtc->pending_async_planes = true; + + if (priv->data->shadow_register) { + mtk_disp_mutex_acquire(mtk_crtc->mutex); + mtk_crtc_ddp_config(crtc); + mtk_disp_mutex_release(mtk_crtc->mutex); + } + mutex_unlock(&mtk_crtc->hw_lock); }
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, @@ -429,6 +490,20 @@ int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, return 0; }
+void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, + struct drm_plane_state *new_state) +{ + struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); + const struct drm_plane_helper_funcs *plane_helper_funcs = + plane->helper_private; + + if (!mtk_crtc->enabled) + return; + + plane_helper_funcs->atomic_update(plane, new_state); + mtk_drm_crtc_hw_config(mtk_crtc); +} + static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { @@ -510,34 +585,14 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); - struct mtk_drm_private *priv = crtc->dev->dev_private; - unsigned int pending_planes = 0; int i;
if (mtk_crtc->event) mtk_crtc->pending_needs_vblank = true; - for (i = 0; i < mtk_crtc->layer_nr; i++) { - struct drm_plane *plane = &mtk_crtc->planes[i]; - struct mtk_plane_state *plane_state; - - plane_state = to_mtk_plane_state(plane->state); - if (plane_state->pending.dirty) { - plane_state->pending.config = true; - plane_state->pending.dirty = false; - pending_planes |= BIT(i); - } - } - if (pending_planes) - mtk_crtc->pending_planes = true; if (crtc->state->color_mgmt_changed) for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); - - if (priv->data->shadow_register) { - mtk_disp_mutex_acquire(mtk_crtc->mutex); - mtk_crtc_ddp_config(crtc); - mtk_disp_mutex_release(mtk_crtc->mutex); - } + mtk_drm_crtc_hw_config(mtk_crtc); }
static const struct drm_crtc_funcs mtk_crtc_funcs = { @@ -729,6 +784,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); priv->num_pipes++; + mutex_init(&mtk_crtc->hw_lock);
return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h index 6afe1c19557a..a2b4677a451c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -21,5 +21,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, unsigned int path_len); int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, struct mtk_plane_state *state); +void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, + struct drm_plane_state *plane_state);
#endif /* MTK_DRM_CRTC_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index cd7c97eb7ee6..a6a7cb1f4eeb 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -7,6 +7,7 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_fourcc.h> +#include <drm/drm_atomic_uapi.h> #include <drm/drm_plane_helper.h> #include <drm/drm_gem_framebuffer_helper.h>
@@ -70,6 +71,50 @@ static void mtk_drm_plane_destroy_state(struct drm_plane *plane, kfree(to_mtk_plane_state(state)); }
+static int mtk_plane_atomic_async_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct drm_crtc_state *crtc_state; + + if (plane != state->crtc->cursor) + return -EINVAL; + + if (!plane->state) + return -EINVAL; + + if (!plane->state->fb) + return -EINVAL; + + if (state->state) + crtc_state = drm_atomic_get_existing_crtc_state(state->state, + state->crtc); + else /* Special case for asynchronous cursor updates. */ + crtc_state = state->crtc->state; + + return drm_atomic_helper_check_plane_state(plane->state, crtc_state, + DRM_PLANE_HELPER_NO_SCALING, + DRM_PLANE_HELPER_NO_SCALING, + true, true); +} + +static void mtk_plane_atomic_async_update(struct drm_plane *plane, + struct drm_plane_state *new_state) +{ + struct mtk_plane_state *state = to_mtk_plane_state(plane->state); + + plane->state->crtc_x = new_state->crtc_x; + plane->state->crtc_y = new_state->crtc_y; + plane->state->crtc_h = new_state->crtc_h; + plane->state->crtc_w = new_state->crtc_w; + plane->state->src_x = new_state->src_x; + plane->state->src_y = new_state->src_y; + plane->state->src_h = new_state->src_h; + plane->state->src_w = new_state->src_w; + state->pending.async_dirty = true; + + mtk_drm_crtc_async_update(new_state->crtc, plane, new_state); +} + static const struct drm_plane_funcs mtk_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, @@ -158,6 +203,8 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = { .atomic_check = mtk_plane_atomic_check, .atomic_update = mtk_plane_atomic_update, .atomic_disable = mtk_plane_atomic_disable, + .atomic_async_update = mtk_plane_atomic_async_update, + .atomic_async_check = mtk_plane_atomic_async_check, };
int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h index 760885e35b27..d454bece9535 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h @@ -22,6 +22,8 @@ struct mtk_plane_pending_state { unsigned int height; unsigned int rotation; bool dirty; + bool async_dirty; + bool async_config; };
struct mtk_plane_state {
Hi, Bibby:
On Thu, 2019-12-05 at 17:27 +0800, Bibby Hsieh wrote:
Support to async updates of cursors by using the new atomic interface for that.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 98 +++++++++++++++++++----- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 + drivers/gpu/drm/mediatek/mtk_drm_plane.c | 47 ++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 + 4 files changed, 128 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 4bc52346093d..e887a6877bcd 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -41,12 +41,16 @@ struct mtk_drm_crtc { struct drm_plane *planes; unsigned int layer_nr; bool pending_planes;
bool pending_async_planes;
void __iomem *config_regs; const struct mtk_mmsys_reg_data *mmsys_reg_data; struct mtk_disp_mutex *mutex; unsigned int ddp_comp_nr; struct mtk_ddp_comp **ddp_comp;
/* lock for display hardware access */
struct mutex hw_lock;
};
struct mtk_crtc_state { @@ -415,6 +419,63 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) } mtk_crtc->pending_planes = false; }
- if (mtk_crtc->pending_async_planes) {
for (i = 0; i < mtk_crtc->layer_nr; i++) {struct drm_plane *plane = &mtk_crtc->planes[i];struct mtk_plane_state *plane_state;plane_state = to_mtk_plane_state(plane->state);if (!plane_state->pending.async_config)continue;comp = mtk_drm_ddp_comp_for_plane(crtc, plane,&local_layer);if (comp)mtk_ddp_comp_layer_config(comp, local_layer,plane_state);plane_state->pending.async_config = false;}mtk_crtc->pending_async_planes = false;- }
+}
+static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) +{
- struct drm_crtc *crtc = &mtk_crtc->base;
- struct mtk_drm_private *priv = crtc->dev->dev_private;
- unsigned int pending_planes = 0, pending_async_planes = 0;
- int i;
- mutex_lock(&mtk_crtc->hw_lock);
- for (i = 0; i < mtk_crtc->layer_nr; i++) {
struct drm_plane *plane = &mtk_crtc->planes[i];struct mtk_plane_state *plane_state;plane_state = to_mtk_plane_state(plane->state);if (plane_state->pending.dirty) {plane_state->pending.config = true;plane_state->pending.dirty = false;pending_planes |= BIT(i);} else if (plane_state->pending.async_dirty) {plane_state->pending.async_config = true;plane_state->pending.async_dirty = false;pending_async_planes |= BIT(i);}- }
- if (pending_planes)
mtk_crtc->pending_planes = true;- if (pending_async_planes)
mtk_crtc->pending_async_planes = true;- if (priv->data->shadow_register) {
mtk_disp_mutex_acquire(mtk_crtc->mutex);mtk_crtc_ddp_config(crtc);mtk_disp_mutex_release(mtk_crtc->mutex);- }
- mutex_unlock(&mtk_crtc->hw_lock);
}
int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, @@ -429,6 +490,20 @@ int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, return 0; }
+void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
struct drm_plane_state *new_state)+{
- struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- const struct drm_plane_helper_funcs *plane_helper_funcs =
plane->helper_private;- if (!mtk_crtc->enabled)
return;- plane_helper_funcs->atomic_update(plane, new_state);
- mtk_drm_crtc_hw_config(mtk_crtc);
+}
static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state) { @@ -510,34 +585,14 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_crtc_state) { struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_drm_private *priv = crtc->dev->dev_private;
unsigned int pending_planes = 0; int i;
if (mtk_crtc->event) mtk_crtc->pending_needs_vblank = true;
for (i = 0; i < mtk_crtc->layer_nr; i++) {
struct drm_plane *plane = &mtk_crtc->planes[i];struct mtk_plane_state *plane_state;plane_state = to_mtk_plane_state(plane->state);if (plane_state->pending.dirty) {plane_state->pending.config = true;plane_state->pending.dirty = false;pending_planes |= BIT(i);}}
if (pending_planes)
mtk_crtc->pending_planes = true;if (crtc->state->color_mgmt_changed) for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
if (priv->data->shadow_register) {
mtk_disp_mutex_acquire(mtk_crtc->mutex);mtk_crtc_ddp_config(crtc);mtk_disp_mutex_release(mtk_crtc->mutex);}
- mtk_drm_crtc_hw_config(mtk_crtc);
}
static const struct drm_crtc_funcs mtk_crtc_funcs = { @@ -729,6 +784,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE); drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE); priv->num_pipes++;
mutex_init(&mtk_crtc->hw_lock);
return 0;
} diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h index 6afe1c19557a..a2b4677a451c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -21,5 +21,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, unsigned int path_len); int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, struct mtk_plane_state *state); +void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
struct drm_plane_state *plane_state);#endif /* MTK_DRM_CRTC_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index cd7c97eb7ee6..a6a7cb1f4eeb 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -7,6 +7,7 @@ #include <drm/drm_atomic.h> #include <drm/drm_atomic_helper.h> #include <drm/drm_fourcc.h> +#include <drm/drm_atomic_uapi.h> #include <drm/drm_plane_helper.h> #include <drm/drm_gem_framebuffer_helper.h>
@@ -70,6 +71,50 @@ static void mtk_drm_plane_destroy_state(struct drm_plane *plane, kfree(to_mtk_plane_state(state)); }
+static int mtk_plane_atomic_async_check(struct drm_plane *plane,
struct drm_plane_state *state)+{
- struct drm_crtc_state *crtc_state;
- if (plane != state->crtc->cursor)
return -EINVAL;- if (!plane->state)
return -EINVAL;- if (!plane->state->fb)
return -EINVAL;- if (state->state)
crtc_state = drm_atomic_get_existing_crtc_state(state->state,state->crtc);- else /* Special case for asynchronous cursor updates. */
crtc_state = state->crtc->state;- return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
DRM_PLANE_HELPER_NO_SCALING,DRM_PLANE_HELPER_NO_SCALING,true, true);+}
+static void mtk_plane_atomic_async_update(struct drm_plane *plane,
struct drm_plane_state *new_state)+{
- struct mtk_plane_state *state = to_mtk_plane_state(plane->state);
- plane->state->crtc_x = new_state->crtc_x;
- plane->state->crtc_y = new_state->crtc_y;
- plane->state->crtc_h = new_state->crtc_h;
- plane->state->crtc_w = new_state->crtc_w;
- plane->state->src_x = new_state->src_x;
- plane->state->src_y = new_state->src_y;
- plane->state->src_h = new_state->src_h;
- plane->state->src_w = new_state->src_w;
- state->pending.async_dirty = true;
- mtk_drm_crtc_async_update(new_state->crtc, plane, new_state);
+}
static const struct drm_plane_funcs mtk_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, @@ -158,6 +203,8 @@ static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = { .atomic_check = mtk_plane_atomic_check, .atomic_update = mtk_plane_atomic_update, .atomic_disable = mtk_plane_atomic_disable,
- .atomic_async_update = mtk_plane_atomic_async_update,
- .atomic_async_check = mtk_plane_atomic_async_check,
};
int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.h b/drivers/gpu/drm/mediatek/mtk_drm_plane.h index 760885e35b27..d454bece9535 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.h @@ -22,6 +22,8 @@ struct mtk_plane_pending_state { unsigned int height; unsigned int rotation; bool dirty;
- bool async_dirty;
- bool async_config;
};
struct mtk_plane_state {
Under shadow register case, we do not disable all the plane before disable all the hardwares. Fix it.
Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index e887a6877bcd..e40c8cf7d74f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -550,6 +550,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, } mtk_crtc->pending_planes = true;
+ mtk_drm_crtc_hw_config(mtk_crtc); /* Wait for planes to be disabled */ drm_crtc_wait_one_vblank(crtc);
On Thu, 2019-12-05 at 17:27 +0800, Bibby Hsieh wrote:
Under shadow register case, we do not disable all the plane before disable all the hardwares. Fix it.
Except the 'Fixes' tag, I could add it,
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index e887a6877bcd..e40c8cf7d74f 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -550,6 +550,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, } mtk_crtc->pending_planes = true;
- mtk_drm_crtc_hw_config(mtk_crtc); /* Wait for planes to be disabled */ drm_crtc_wait_one_vblank(crtc);
layer_on and layer_off both are unused external function, remove them from mtk_ddp_comp_funcs structure.
Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com Reviewed-by: CK Hu ck.hu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 -- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 16 ---------------- 2 files changed, 18 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 722a5adb79dc..8a32248671c3 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -314,8 +314,6 @@ static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { .disable_vblank = mtk_ovl_disable_vblank, .supported_rotations = mtk_ovl_supported_rotations, .layer_nr = mtk_ovl_layer_nr, - .layer_on = mtk_ovl_layer_on, - .layer_off = mtk_ovl_layer_off, .layer_check = mtk_ovl_layer_check, .layer_config = mtk_ovl_layer_config, .bgclr_in_on = mtk_ovl_bgclr_in_on, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 19a955ab0748..dbfb90e9b9cf 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -81,8 +81,6 @@ struct mtk_ddp_comp_funcs { void (*unprepare)(struct mtk_ddp_comp *comp); unsigned int (*supported_rotations)(struct mtk_ddp_comp *comp); unsigned int (*layer_nr)(struct mtk_ddp_comp *comp); - void (*layer_on)(struct mtk_ddp_comp *comp, unsigned int idx); - void (*layer_off)(struct mtk_ddp_comp *comp, unsigned int idx); int (*layer_check)(struct mtk_ddp_comp *comp, unsigned int idx, struct mtk_plane_state *state); @@ -165,20 +163,6 @@ static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp) return 0; }
-static inline void mtk_ddp_comp_layer_on(struct mtk_ddp_comp *comp, - unsigned int idx) -{ - if (comp->funcs && comp->funcs->layer_on) - comp->funcs->layer_on(comp, idx); -} - -static inline void mtk_ddp_comp_layer_off(struct mtk_ddp_comp *comp, - unsigned int idx) -{ - if (comp->funcs && comp->funcs->layer_off) - comp->funcs->layer_off(comp, idx); -} - static inline int mtk_ddp_comp_layer_check(struct mtk_ddp_comp *comp, unsigned int idx, struct mtk_plane_state *state)
The CMDQ (Command Queue) in MT8183 is used to help update all relevant display controller registers with critical time limation. This patch add cmdq interface in ddp_comp interface, let all ddp_comp interface can support cpu/cmdq function at the same time.
Signed-off-by: YT Shen yt.shen@mediatek.com Signed-off-by: CK Hu ck.hu@mediatek.com Signed-off-by: Philipp Zabel p.zabel@pengutronix.de Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 65 +++++----- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 43 ++++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 132 +++++++++++++++----- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 31 +++-- 6 files changed, 194 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index 59de2a46aa49..6fb0d6983a4a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -9,6 +9,7 @@ #include <linux/of_device.h> #include <linux/of_irq.h> #include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -45,12 +46,12 @@ static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_color *color = comp_to_color(comp);
- writel(w, comp->regs + DISP_COLOR_WIDTH(color)); - writel(h, comp->regs + DISP_COLOR_HEIGHT(color)); + mtk_ddp_write(cmdq_pkt, w, comp, DISP_COLOR_WIDTH(color)); + mtk_ddp_write(cmdq_pkt, h, comp, DISP_COLOR_HEIGHT(color)); }
static void mtk_color_start(struct mtk_ddp_comp *comp) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 8a32248671c3..649e371dd9b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -12,6 +12,7 @@ #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -125,14 +126,15 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { if (w != 0 && h != 0) - writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE); - writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR); + mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp, + DISP_REG_OVL_ROI_SIZE); + mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);
- writel(0x1, comp->regs + DISP_REG_OVL_RST); - writel(0x0, comp->regs + DISP_REG_OVL_RST); + mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST); + mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST); }
static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) @@ -176,16 +178,16 @@ static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx, return 0; }
-static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) +static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx, + struct cmdq_pkt *cmdq_pkt) { - unsigned int reg; unsigned int gmc_thrshd_l; unsigned int gmc_thrshd_h; unsigned int gmc_value; struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
- writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); - + mtk_ddp_write(cmdq_pkt, 0x1, comp, + DISP_REG_OVL_RDMA_CTRL(idx)); gmc_thrshd_l = GMC_THRESHOLD_LOW >> (GMC_THRESHOLD_BITS - ovl->data->gmc_bits); gmc_thrshd_h = GMC_THRESHOLD_HIGH >> @@ -195,22 +197,19 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) else gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | gmc_thrshd_h << 16 | gmc_thrshd_h << 24; - writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx)); - - reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); - reg = reg | BIT(idx); - writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); + mtk_ddp_write(cmdq_pkt, gmc_value, + comp, DISP_REG_OVL_RDMA_GMC(idx)); + mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp, + DISP_REG_OVL_SRC_CON, BIT(idx)); }
-static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx) +static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx, + struct cmdq_pkt *cmdq_pkt) { - unsigned int reg; - - reg = readl(comp->regs + DISP_REG_OVL_SRC_CON); - reg = reg & ~BIT(idx); - writel(reg, comp->regs + DISP_REG_OVL_SRC_CON); - - writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx)); + mtk_ddp_write_mask(cmdq_pkt, 0, comp, + DISP_REG_OVL_SRC_CON, BIT(idx)); + mtk_ddp_write(cmdq_pkt, 0, comp, + DISP_REG_OVL_RDMA_CTRL(idx)); }
static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) @@ -250,7 +249,8 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) }
static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, - struct mtk_plane_state *state) + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_ovl *ovl = comp_to_ovl(comp); struct mtk_plane_pending_state *pending = &state->pending; @@ -262,7 +262,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, unsigned int con;
if (!pending->enable) - mtk_ovl_layer_off(comp, idx); + mtk_ovl_layer_off(comp, idx, cmdq_pkt);
con = ovl_fmt_convert(ovl, fmt); if (idx != 0) @@ -278,14 +278,19 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, addr += pending->pitch - 1; }
- writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx)); - writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx)); - writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx)); - writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx)); - writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx)); + mtk_ddp_write_relaxed(cmdq_pkt, con, comp, + DISP_REG_OVL_CON(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, + DISP_REG_OVL_PITCH(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp, + DISP_REG_OVL_SRC_SIZE(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, offset, comp, + DISP_REG_OVL_OFFSET(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, + DISP_REG_OVL_ADDR(ovl, idx));
if (pending->enable) - mtk_ovl_layer_on(comp, idx); + mtk_ovl_layer_on(comp, idx, cmdq_pkt); }
static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 15cc4ae84aee..c1abde3743bf 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -10,6 +10,7 @@ #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -127,15 +128,17 @@ static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, unsigned int height, unsigned int vrefresh, - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { unsigned int threshold; unsigned int reg; struct mtk_disp_rdma *rdma = comp_to_rdma(comp); u32 rdma_fifo_size;
- rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width); - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height); + mtk_ddp_write_mask(cmdq_pkt, width, comp, + DISP_REG_RDMA_SIZE_CON_0, 0xfff); + mtk_ddp_write_mask(cmdq_pkt, height, comp, + DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
if (rdma->fifo_size) rdma_fifo_size = rdma->fifo_size; @@ -152,7 +155,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); - writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); + mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON); }
static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, @@ -198,7 +201,8 @@ static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp) }
static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, - struct mtk_plane_state *state) + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_rdma *rdma = comp_to_rdma(comp); struct mtk_plane_pending_state *pending = &state->pending; @@ -208,24 +212,27 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, unsigned int con;
con = rdma_fmt_convert(rdma, fmt); - writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON); + mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON);
if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) { - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, - RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE); - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, - RDMA_MATRIX_INT_MTX_SEL, - RDMA_MATRIX_INT_MTX_BT601_to_RGB); + mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp, + DISP_REG_RDMA_SIZE_CON_0, + RDMA_MATRIX_ENABLE); + mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB, + comp, DISP_REG_RDMA_SIZE_CON_0, + RDMA_MATRIX_INT_MTX_SEL); } else { - rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, - RDMA_MATRIX_ENABLE, 0); + mtk_ddp_write_mask(cmdq_pkt, 0, comp, + DISP_REG_RDMA_SIZE_CON_0, + RDMA_MATRIX_ENABLE); } + mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR); + mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH); + mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp, + DISP_RDMA_MEM_GMC_SETTING_0); + mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp, + DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
- writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR); - writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH); - writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0); - rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, - RDMA_MODE_MEMORY, RDMA_MODE_MEMORY); }
static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index e40c8cf7d74f..8c6231ed6f55 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -312,7 +312,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) if (prev == DDP_COMPONENT_OVL0) mtk_ddp_comp_bgclr_in_on(comp);
- mtk_ddp_comp_config(comp, width, height, vrefresh, bpc); + mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); mtk_ddp_comp_start(comp); }
@@ -327,7 +327,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); if (comp) mtk_ddp_comp_layer_config(comp, local_layer, - plane_state); + plane_state, NULL); }
return 0; @@ -394,7 +394,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) if (state->pending_config) { mtk_ddp_comp_config(comp, state->pending_width, state->pending_height, - state->pending_vrefresh, 0); + state->pending_vrefresh, 0, NULL);
state->pending_config = false; } @@ -414,7 +414,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
if (comp) mtk_ddp_comp_layer_config(comp, local_layer, - plane_state); + plane_state, NULL); plane_state->pending.config = false; } mtk_crtc->pending_planes = false; @@ -435,7 +435,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
if (comp) mtk_ddp_comp_layer_config(comp, local_layer, - plane_state); + plane_state, NULL); plane_state->pending.async_config = false; } mtk_crtc->pending_async_planes = false; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 3407d38aff8f..f967b749e1a3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -12,7 +12,8 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/platform_device.h> - +#include <drm/drmP.h> +#include <linux/soc/mediatek/mtk-cmdq.h> #include "mtk_drm_drv.h" #include "mtk_drm_plane.h" #include "mtk_drm_ddp_comp.h" @@ -76,36 +77,84 @@ #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) #define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
+void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, unsigned int offset) +{ +#ifdef CONFIG_MTK_CMDQ + if (cmdq_pkt) + cmdq_pkt_write(cmdq_pkt, comp->subsys, + comp->regs_pa + offset, value); + else +#endif + writel(value, comp->regs + offset); +} + +void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, + unsigned int offset) +{ +#ifdef CONFIG_MTK_CMDQ + if (cmdq_pkt) + cmdq_pkt_write(cmdq_pkt, comp->subsys, + comp->regs_pa + offset, value); + else +#endif + writel_relaxed(value, comp->regs + offset); +} + +void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, + unsigned int value, + struct mtk_ddp_comp *comp, + unsigned int offset, + unsigned int mask) +{ +#ifdef CONFIG_MTK_CMDQ + if (cmdq_pkt) { + cmdq_pkt_write_mask(cmdq_pkt, comp->subsys, + comp->regs_pa + offset, value, mask); + } else { +#endif + u32 tmp = readl(comp->regs + offset); + + tmp = (tmp & ~mask) | (value & mask); + writel(tmp, comp->regs + offset); +#ifdef CONFIG_MTK_CMDQ + } +#endif +} + void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, - unsigned int CFG) + unsigned int CFG, struct cmdq_pkt *cmdq_pkt) { /* If bpc equal to 0, the dithering function didn't be enabled */ if (bpc == 0) return;
if (bpc >= MTK_MIN_BPC) { - writel(0, comp->regs + DISP_DITHER_5); - writel(0, comp->regs + DISP_DITHER_7); - writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | - DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | - DITHER_NEW_BIT_MODE, - comp->regs + DISP_DITHER_15); - writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | - DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | - DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | - DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), - comp->regs + DISP_DITHER_16); - writel(DISP_DITHERING, comp->regs + CFG); + mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5); + mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7); + mtk_ddp_write(cmdq_pkt, + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | + DITHER_NEW_BIT_MODE, + comp, DISP_DITHER_15); + mtk_ddp_write(cmdq_pkt, + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), + comp, DISP_DITHER_16); + mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG); } }
static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - writel(w << 16 | h, comp->regs + DISP_OD_SIZE); - writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG); - mtk_dither_set(comp, bpc, DISP_OD_CFG); + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE); + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG); + mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt); }
static void mtk_od_start(struct mtk_ddp_comp *comp) @@ -120,9 +169,9 @@ static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - writel(h << 16 | w, comp->regs + DISP_AAL_SIZE); + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE); }
static void mtk_aal_start(struct mtk_ddp_comp *comp) @@ -137,10 +186,10 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp)
static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - writel(h << 16 | w, comp->regs + DISP_CCORR_SIZE); - writel(CCORR_RELAY_MODE, comp->regs + DISP_CCORR_CFG); + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE); + mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG); }
static void mtk_ccorr_start(struct mtk_ddp_comp *comp) @@ -155,10 +204,10 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - writel(h << 16 | w, comp->regs + DISP_DITHER_SIZE); - writel(DITHER_RELAY_MODE, comp->regs + DISP_DITHER_CFG); + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE); + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG); }
static void mtk_dither_start(struct mtk_ddp_comp *comp) @@ -173,10 +222,10 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp)
static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh, - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { - writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE); - mtk_dither_set(comp, bpc, DISP_GAMMA_CFG); + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE); + mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt); }
static void mtk_gamma_start(struct mtk_ddp_comp *comp) @@ -324,6 +373,9 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, const struct mtk_ddp_comp_funcs *funcs) { struct platform_device *comp_pdev; + struct resource res; + struct cmdq_client_reg cmdq_reg; + int ret = 0;
if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) return -EINVAL; @@ -358,6 +410,28 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, } comp->dev = &comp_pdev->dev;
+#ifdef CONFIG_MTK_CMDQ + if (of_address_to_resource(node, 0, &res) != 0) { + dev_err(dev, "Missing reg in %s node\n", + node->full_name); + return -EINVAL; + } + comp->regs_pa = res.start; + + comp_pdev = of_find_device_by_node(node); + if (!comp_pdev) { + dev_warn(dev, "Waiting for component device %s\n", + node->full_name); + return -EPROBE_DEFER; + } + + ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, 0); + if (ret != 0) + dev_dbg(&comp_pdev->dev, + "get mediatek,gce-client-reg fail!\n"); + else + comp->subsys = cmdq_reg.subsys; +#endif return 0; }
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index dbfb90e9b9cf..384abae5a8c8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -69,10 +69,11 @@ enum mtk_ddp_comp_id { };
struct mtk_ddp_comp; - +struct cmdq_pkt; struct mtk_ddp_comp_funcs { void (*config)(struct mtk_ddp_comp *comp, unsigned int w, - unsigned int h, unsigned int vrefresh, unsigned int bpc); + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void (*start)(struct mtk_ddp_comp *comp); void (*stop)(struct mtk_ddp_comp *comp); void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc); @@ -85,7 +86,8 @@ struct mtk_ddp_comp_funcs { unsigned int idx, struct mtk_plane_state *state); void (*layer_config)(struct mtk_ddp_comp *comp, unsigned int idx, - struct mtk_plane_state *state); + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt); void (*gamma_set)(struct mtk_ddp_comp *comp, struct drm_crtc_state *state); void (*bgclr_in_on)(struct mtk_ddp_comp *comp); @@ -99,14 +101,17 @@ struct mtk_ddp_comp { struct device *dev; enum mtk_ddp_comp_id id; const struct mtk_ddp_comp_funcs *funcs; + resource_size_t regs_pa; + u8 subsys; };
static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, - unsigned int vrefresh, unsigned int bpc) + unsigned int vrefresh, unsigned int bpc, + struct cmdq_pkt *cmdq_pkt) { if (comp->funcs && comp->funcs->config) - comp->funcs->config(comp, w, h, vrefresh, bpc); + comp->funcs->config(comp, w, h, vrefresh, bpc, cmdq_pkt); }
static inline void mtk_ddp_comp_prepare(struct mtk_ddp_comp *comp) @@ -174,10 +179,11 @@ static inline int mtk_ddp_comp_layer_check(struct mtk_ddp_comp *comp,
static inline void mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, - struct mtk_plane_state *state) + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) { if (comp->funcs && comp->funcs->layer_config) - comp->funcs->layer_config(comp, idx, state); + comp->funcs->layer_config(comp, idx, state, cmdq_pkt); }
static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, @@ -207,6 +213,13 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp); void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp); void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc, - unsigned int CFG); - + unsigned int CFG, struct cmdq_pkt *cmdq_pkt); +enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id); +void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, unsigned int offset); +void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, unsigned int offset); +void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, unsigned int offset, + unsigned int mask); #endif /* MTK_DRM_DDP_COMP_H */
Hi, Bibby:
On Thu, 2019-12-05 at 17:27 +0800, Bibby Hsieh wrote:
The CMDQ (Command Queue) in MT8183 is used to help update all relevant display controller registers with critical time limation. This patch add cmdq interface in ddp_comp interface, let all ddp_comp interface can support cpu/cmdq function at the same time.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: YT Shen yt.shen@mediatek.com Signed-off-by: CK Hu ck.hu@mediatek.com Signed-off-by: Philipp Zabel p.zabel@pengutronix.de Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com
drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 65 +++++----- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 43 ++++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 10 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 132 +++++++++++++++----- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 31 +++-- 6 files changed, 194 insertions(+), 94 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c index 59de2a46aa49..6fb0d6983a4a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c @@ -9,6 +9,7 @@ #include <linux/of_device.h> #include <linux/of_irq.h> #include <linux/platform_device.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -45,12 +46,12 @@ static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh,
unsigned int bpc)
unsigned int bpc, struct cmdq_pkt *cmdq_pkt){ struct mtk_disp_color *color = comp_to_color(comp);
- writel(w, comp->regs + DISP_COLOR_WIDTH(color));
- writel(h, comp->regs + DISP_COLOR_HEIGHT(color));
- mtk_ddp_write(cmdq_pkt, w, comp, DISP_COLOR_WIDTH(color));
- mtk_ddp_write(cmdq_pkt, h, comp, DISP_COLOR_HEIGHT(color));
}
static void mtk_color_start(struct mtk_ddp_comp *comp) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 8a32248671c3..649e371dd9b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -12,6 +12,7 @@ #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -125,14 +126,15 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh,
unsigned int bpc)
unsigned int bpc, struct cmdq_pkt *cmdq_pkt){ if (w != 0 && h != 0)
writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);- writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR);
mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp,DISP_REG_OVL_ROI_SIZE);- mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);
- writel(0x1, comp->regs + DISP_REG_OVL_RST);
- writel(0x0, comp->regs + DISP_REG_OVL_RST);
- mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST);
- mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST);
}
static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) @@ -176,16 +178,16 @@ static int mtk_ovl_layer_check(struct mtk_ddp_comp *comp, unsigned int idx, return 0; }
-static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) +static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
struct cmdq_pkt *cmdq_pkt){
unsigned int reg; unsigned int gmc_thrshd_l; unsigned int gmc_thrshd_h; unsigned int gmc_value; struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
- mtk_ddp_write(cmdq_pkt, 0x1, comp,
DISP_REG_OVL_RDMA_CTRL(idx));@@ -195,22 +197,19 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) else gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 | gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
- writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
- reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
- reg = reg | BIT(idx);
- writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
- mtk_ddp_write(cmdq_pkt, gmc_value,
comp, DISP_REG_OVL_RDMA_GMC(idx));- mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp,
DISP_REG_OVL_SRC_CON, BIT(idx));}
-static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx) +static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,
struct cmdq_pkt *cmdq_pkt){
- unsigned int reg;
- reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
- reg = reg & ~BIT(idx);
- writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
- writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
- mtk_ddp_write_mask(cmdq_pkt, 0, comp,
DISP_REG_OVL_SRC_CON, BIT(idx));- mtk_ddp_write(cmdq_pkt, 0, comp,
DISP_REG_OVL_RDMA_CTRL(idx));}
static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) @@ -250,7 +249,8 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt) }
static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
struct mtk_plane_state *state)
struct mtk_plane_state *state,struct cmdq_pkt *cmdq_pkt){ struct mtk_disp_ovl *ovl = comp_to_ovl(comp); struct mtk_plane_pending_state *pending = &state->pending; @@ -262,7 +262,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, unsigned int con;
if (!pending->enable)
mtk_ovl_layer_off(comp, idx);
mtk_ovl_layer_off(comp, idx, cmdq_pkt);con = ovl_fmt_convert(ovl, fmt); if (idx != 0)
@@ -278,14 +278,19 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, addr += pending->pitch - 1; }
- writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx));
- writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
- writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
- writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
- writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx));
mtk_ddp_write_relaxed(cmdq_pkt, con, comp,
DISP_REG_OVL_CON(idx));mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp,
DISP_REG_OVL_PITCH(idx));mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp,
DISP_REG_OVL_SRC_SIZE(idx));mtk_ddp_write_relaxed(cmdq_pkt, offset, comp,
DISP_REG_OVL_OFFSET(idx));mtk_ddp_write_relaxed(cmdq_pkt, addr, comp,
DISP_REG_OVL_ADDR(ovl, idx));if (pending->enable)
mtk_ovl_layer_on(comp, idx);
mtk_ovl_layer_on(comp, idx, cmdq_pkt);}
static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index 15cc4ae84aee..c1abde3743bf 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -10,6 +10,7 @@ #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h" #include "mtk_drm_ddp_comp.h" @@ -127,15 +128,17 @@ static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, unsigned int height, unsigned int vrefresh,
unsigned int bpc)
unsigned int bpc, struct cmdq_pkt *cmdq_pkt){ unsigned int threshold; unsigned int reg; struct mtk_disp_rdma *rdma = comp_to_rdma(comp); u32 rdma_fifo_size;
- rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
- rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
mtk_ddp_write_mask(cmdq_pkt, width, comp,
DISP_REG_RDMA_SIZE_CON_0, 0xfff);mtk_ddp_write_mask(cmdq_pkt, height, comp,
DISP_REG_RDMA_SIZE_CON_1, 0xfffff);if (rdma->fifo_size) rdma_fifo_size = rdma->fifo_size;
@@ -152,7 +155,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
- writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
- mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON);
}
static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma, @@ -198,7 +201,8 @@ static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp) }
static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
struct mtk_plane_state *state)
struct mtk_plane_state *state,struct cmdq_pkt *cmdq_pkt){ struct mtk_disp_rdma *rdma = comp_to_rdma(comp); struct mtk_plane_pending_state *pending = &state->pending; @@ -208,24 +212,27 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx, unsigned int con;
con = rdma_fmt_convert(rdma, fmt);
- writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON);
if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE);rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,RDMA_MATRIX_INT_MTX_SEL,RDMA_MATRIX_INT_MTX_BT601_to_RGB);
mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp,DISP_REG_RDMA_SIZE_CON_0,RDMA_MATRIX_ENABLE);mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,comp, DISP_REG_RDMA_SIZE_CON_0,RDMA_MATRIX_INT_MTX_SEL);
rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,RDMA_MATRIX_ENABLE, 0);
mtk_ddp_write_mask(cmdq_pkt, 0, comp,DISP_REG_RDMA_SIZE_CON_0,RDMA_MATRIX_ENABLE);- mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR);
- mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH);
- mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp,
DISP_RDMA_MEM_GMC_SETTING_0);- mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp,
DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
- writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
- writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
- writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
- rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);}
static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index e40c8cf7d74f..8c6231ed6f55 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -312,7 +312,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) if (prev == DDP_COMPONENT_OVL0) mtk_ddp_comp_bgclr_in_on(comp);
mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);
mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);@@ -327,7 +327,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); if (comp) mtk_ddp_comp_layer_config(comp, local_layer,
plane_state);
plane_state, NULL);}
return 0;
@@ -394,7 +394,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) if (state->pending_config) { mtk_ddp_comp_config(comp, state->pending_width, state->pending_height,
state->pending_vrefresh, 0);
state->pending_vrefresh, 0, NULL);state->pending_config = false; }
@@ -414,7 +414,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
if (comp) mtk_ddp_comp_layer_config(comp, local_layer,
plane_state);
plane_state, NULL); plane_state->pending.config = false;@@ -435,7 +435,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
if (comp) mtk_ddp_comp_layer_config(comp, local_layer,
plane_state);
plane_state, NULL); plane_state->pending.async_config = false;diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 3407d38aff8f..f967b749e1a3 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -12,7 +12,8 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/platform_device.h>
+#include <drm/drmP.h> +#include <linux/soc/mediatek/mtk-cmdq.h> #include "mtk_drm_drv.h" #include "mtk_drm_plane.h" #include "mtk_drm_ddp_comp.h" @@ -76,36 +77,84 @@ #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) #define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
+void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp, unsigned int offset)+{ +#ifdef CONFIG_MTK_CMDQ
- if (cmdq_pkt)
cmdq_pkt_write(cmdq_pkt, comp->subsys,comp->regs_pa + offset, value);- else
+#endif
writel(value, comp->regs + offset);+}
+void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp,unsigned int offset)+{ +#ifdef CONFIG_MTK_CMDQ
- if (cmdq_pkt)
cmdq_pkt_write(cmdq_pkt, comp->subsys,comp->regs_pa + offset, value);- else
+#endif
writel_relaxed(value, comp->regs + offset);+}
+void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt,
unsigned int value,struct mtk_ddp_comp *comp,unsigned int offset,unsigned int mask)+{ +#ifdef CONFIG_MTK_CMDQ
- if (cmdq_pkt) {
cmdq_pkt_write_mask(cmdq_pkt, comp->subsys,comp->regs_pa + offset, value, mask);- } else {
+#endif
u32 tmp = readl(comp->regs + offset);tmp = (tmp & ~mask) | (value & mask);writel(tmp, comp->regs + offset);+#ifdef CONFIG_MTK_CMDQ
- }
+#endif +}
void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
unsigned int CFG)
unsigned int CFG, struct cmdq_pkt *cmdq_pkt){ /* If bpc equal to 0, the dithering function didn't be enabled */ if (bpc == 0) return;
if (bpc >= MTK_MIN_BPC) {
writel(0, comp->regs + DISP_DITHER_5);writel(0, comp->regs + DISP_DITHER_7);writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |DITHER_NEW_BIT_MODE,comp->regs + DISP_DITHER_15);writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),comp->regs + DISP_DITHER_16);writel(DISP_DITHERING, comp->regs + CFG);
mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |DITHER_NEW_BIT_MODE,comp, DISP_DITHER_15);mtk_ddp_write(cmdq_pkt,DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),comp, DISP_DITHER_16);mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);}
static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh,
unsigned int bpc)
unsigned int bpc, struct cmdq_pkt *cmdq_pkt){
- writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
- writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG);
- mtk_dither_set(comp, bpc, DISP_OD_CFG);
- mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE);
- mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG);
- mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
}
static void mtk_od_start(struct mtk_ddp_comp *comp) @@ -120,9 +169,9 @@ static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh,
unsigned int bpc)
unsigned int bpc, struct cmdq_pkt *cmdq_pkt){
- writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
}
static void mtk_aal_start(struct mtk_ddp_comp *comp) @@ -137,10 +186,10 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp)
static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh,
unsigned int bpc)
unsigned int bpc, struct cmdq_pkt *cmdq_pkt){
- writel(h << 16 | w, comp->regs + DISP_CCORR_SIZE);
- writel(CCORR_RELAY_MODE, comp->regs + DISP_CCORR_CFG);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
- mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
}
static void mtk_ccorr_start(struct mtk_ddp_comp *comp) @@ -155,10 +204,10 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh,
unsigned int bpc)
unsigned int bpc, struct cmdq_pkt *cmdq_pkt){
- writel(h << 16 | w, comp->regs + DISP_DITHER_SIZE);
- writel(DITHER_RELAY_MODE, comp->regs + DISP_DITHER_CFG);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE);
- mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG);
}
static void mtk_dither_start(struct mtk_ddp_comp *comp) @@ -173,10 +222,10 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp)
static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h, unsigned int vrefresh,
unsigned int bpc)
unsigned int bpc, struct cmdq_pkt *cmdq_pkt){
- writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE);
- mtk_dither_set(comp, bpc, DISP_GAMMA_CFG);
- mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
- mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
}
static void mtk_gamma_start(struct mtk_ddp_comp *comp) @@ -324,6 +373,9 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, const struct mtk_ddp_comp_funcs *funcs) { struct platform_device *comp_pdev;
struct resource res;
struct cmdq_client_reg cmdq_reg;
int ret = 0;
if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX) return -EINVAL;
@@ -358,6 +410,28 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, } comp->dev = &comp_pdev->dev;
+#ifdef CONFIG_MTK_CMDQ
- if (of_address_to_resource(node, 0, &res) != 0) {
dev_err(dev, "Missing reg in %s node\n",node->full_name);return -EINVAL;- }
- comp->regs_pa = res.start;
- comp_pdev = of_find_device_by_node(node);
- if (!comp_pdev) {
dev_warn(dev, "Waiting for component device %s\n",node->full_name);return -EPROBE_DEFER;- }
- ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, 0);
- if (ret != 0)
dev_dbg(&comp_pdev->dev,"get mediatek,gce-client-reg fail!\n");- else
comp->subsys = cmdq_reg.subsys;+#endif return 0; }
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index dbfb90e9b9cf..384abae5a8c8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -69,10 +69,11 @@ enum mtk_ddp_comp_id { };
struct mtk_ddp_comp;
+struct cmdq_pkt; struct mtk_ddp_comp_funcs { void (*config)(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh, unsigned int bpc);
unsigned int h, unsigned int vrefresh,unsigned int bpc, struct cmdq_pkt *cmdq_pkt);@@ -85,7 +86,8 @@ struct mtk_ddp_comp_funcs { unsigned int idx, struct mtk_plane_state *state); void (*layer_config)(struct mtk_ddp_comp *comp, unsigned int idx,
struct mtk_plane_state *state);
struct mtk_plane_state *state,struct cmdq_pkt *cmdq_pkt);@@ -99,14 +101,17 @@ struct mtk_ddp_comp { struct device *dev; enum mtk_ddp_comp_id id; const struct mtk_ddp_comp_funcs *funcs;
- resource_size_t regs_pa;
- u8 subsys;
};
static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp, unsigned int w, unsigned int h,
unsigned int vrefresh, unsigned int bpc)
unsigned int vrefresh, unsigned int bpc,struct cmdq_pkt *cmdq_pkt){ if (comp->funcs && comp->funcs->config)
comp->funcs->config(comp, w, h, vrefresh, bpc);
comp->funcs->config(comp, w, h, vrefresh, bpc, cmdq_pkt);}
static inline void mtk_ddp_comp_prepare(struct mtk_ddp_comp *comp) @@ -174,10 +179,11 @@ static inline int mtk_ddp_comp_layer_check(struct mtk_ddp_comp *comp,
static inline void mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
struct mtk_plane_state *state)
struct mtk_plane_state *state,struct cmdq_pkt *cmdq_pkt){ if (comp->funcs && comp->funcs->layer_config)
comp->funcs->layer_config(comp, idx, state);
comp->funcs->layer_config(comp, idx, state, cmdq_pkt);}
static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, @@ -207,6 +213,13 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp); void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp); void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
unsigned int CFG);
unsigned int CFG, struct cmdq_pkt *cmdq_pkt);+enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id); +void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp, unsigned int offset);+void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp, unsigned int offset);+void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
struct mtk_ddp_comp *comp, unsigned int offset,unsigned int mask);#endif /* MTK_DRM_DDP_COMP_H */
Unlike other SoCs, MT8183 does not have "shadow" registers for performaing an atomic video mode set or page flip at vblank/vsync.
The CMDQ (Commend Queue) in MT8183 is used to help update all relevant display controller registers with critical time limation.
Signed-off-by: YT Shen yt.shen@mediatek.com Signed-off-by: CK Hu ck.hu@mediatek.com Signed-off-by: Philipp Zabel p.zabel@pengutronix.de Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 56 +++++++++++++++++++++---- 1 file changed, 49 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 8c6231ed6f55..496dffe962af 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -12,6 +12,8 @@ #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> #include <drm/drm_vblank.h> +#include <linux/of_address.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_drv.h" #include "mtk_drm_crtc.h" @@ -43,6 +45,9 @@ struct mtk_drm_crtc { bool pending_planes; bool pending_async_planes;
+ struct cmdq_client *cmdq_client; + u32 cmdq_event; + void __iomem *config_regs; const struct mtk_mmsys_reg_data *mmsys_reg_data; struct mtk_disp_mutex *mutex; @@ -234,6 +239,13 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, return NULL; }
+#ifdef CONFIG_MTK_CMDQ +static void ddp_cmdq_cb(struct cmdq_cb_data data) +{ + cmdq_pkt_destroy(data.data); +} +#endif + static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) { struct drm_crtc *crtc = &mtk_crtc->base; @@ -378,7 +390,8 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) } }
-static void mtk_crtc_ddp_config(struct drm_crtc *crtc) +static void mtk_crtc_ddp_config(struct drm_crtc *crtc, + struct cmdq_pkt *cmdq_handle) { struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); @@ -394,7 +407,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) if (state->pending_config) { mtk_ddp_comp_config(comp, state->pending_width, state->pending_height, - state->pending_vrefresh, 0, NULL); + state->pending_vrefresh, 0, + cmdq_handle);
state->pending_config = false; } @@ -414,7 +428,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
if (comp) mtk_ddp_comp_layer_config(comp, local_layer, - plane_state, NULL); + plane_state, + cmdq_handle); plane_state->pending.config = false; } mtk_crtc->pending_planes = false; @@ -435,7 +450,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
if (comp) mtk_ddp_comp_layer_config(comp, local_layer, - plane_state, NULL); + plane_state, + cmdq_handle); plane_state->pending.async_config = false; } mtk_crtc->pending_async_planes = false; @@ -444,6 +460,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) { + struct cmdq_pkt *cmdq_handle; struct drm_crtc *crtc = &mtk_crtc->base; struct mtk_drm_private *priv = crtc->dev->dev_private; unsigned int pending_planes = 0, pending_async_planes = 0; @@ -472,9 +489,18 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
if (priv->data->shadow_register) { mtk_disp_mutex_acquire(mtk_crtc->mutex); - mtk_crtc_ddp_config(crtc); + mtk_crtc_ddp_config(crtc, NULL); mtk_disp_mutex_release(mtk_crtc->mutex); } +#ifdef CONFIG_MTK_CMDQ + if (mtk_crtc->cmdq_client) { + cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); + cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); + cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event); + mtk_crtc_ddp_config(crtc, cmdq_handle); + cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); + } +#endif mutex_unlock(&mtk_crtc->hw_lock); }
@@ -643,8 +669,8 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_drm_private *priv = crtc->dev->dev_private;
- if (!priv->data->shadow_register) - mtk_crtc_ddp_config(crtc); + if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) + mtk_crtc_ddp_config(crtc, NULL);
mtk_drm_finish_page_flip(mtk_crtc); } @@ -787,5 +813,21 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, priv->num_pipes++; mutex_init(&mtk_crtc->hw_lock);
+#ifdef CONFIG_MTK_CMDQ + mtk_crtc->cmdq_client = + cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base), + 2000); + if (IS_ERR(mtk_crtc->cmdq_client)) { + dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", + drm_crtc_index(&mtk_crtc->base)); + mtk_crtc->cmdq_client = NULL; + } + ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events", + drm_crtc_index(&mtk_crtc->base), + &mtk_crtc->cmdq_event); + if (ret) + dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", + drm_crtc_index(&mtk_crtc->base)); +#endif return 0; }
Hi, Bibby:
On Thu, 2019-12-05 at 17:27 +0800, Bibby Hsieh wrote:
Unlike other SoCs, MT8183 does not have "shadow" registers for performaing an atomic video mode set or page flip at vblank/vsync.
The CMDQ (Commend Queue) in MT8183 is used to help update all relevant display controller registers with critical time limation.
Reviewed-by: CK Hu ck.hu@mediatek.com
Signed-off-by: YT Shen yt.shen@mediatek.com Signed-off-by: CK Hu ck.hu@mediatek.com Signed-off-by: Philipp Zabel p.zabel@pengutronix.de Signed-off-by: Bibby Hsieh bibby.hsieh@mediatek.com Signed-off-by: Yongqiang Niu yongqiang.niu@mediatek.com
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 56 +++++++++++++++++++++---- 1 file changed, 49 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 8c6231ed6f55..496dffe962af 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -12,6 +12,8 @@ #include <drm/drm_plane_helper.h> #include <drm/drm_probe_helper.h> #include <drm/drm_vblank.h> +#include <linux/of_address.h> +#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_drv.h" #include "mtk_drm_crtc.h" @@ -43,6 +45,9 @@ struct mtk_drm_crtc { bool pending_planes; bool pending_async_planes;
- struct cmdq_client *cmdq_client;
- u32 cmdq_event;
- void __iomem *config_regs; const struct mtk_mmsys_reg_data *mmsys_reg_data; struct mtk_disp_mutex *mutex;
@@ -234,6 +239,13 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, return NULL; }
+#ifdef CONFIG_MTK_CMDQ +static void ddp_cmdq_cb(struct cmdq_cb_data data) +{
- cmdq_pkt_destroy(data.data);
+} +#endif
static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) { struct drm_crtc *crtc = &mtk_crtc->base; @@ -378,7 +390,8 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) } }
-static void mtk_crtc_ddp_config(struct drm_crtc *crtc) +static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
struct cmdq_pkt *cmdq_handle){ struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); @@ -394,7 +407,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) if (state->pending_config) { mtk_ddp_comp_config(comp, state->pending_width, state->pending_height,
state->pending_vrefresh, 0, NULL);
state->pending_vrefresh, 0,cmdq_handle);state->pending_config = false; }
@@ -414,7 +428,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
if (comp) mtk_ddp_comp_layer_config(comp, local_layer,
plane_state, NULL);
plane_state,cmdq_handle); plane_state->pending.config = false;@@ -435,7 +450,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
if (comp) mtk_ddp_comp_layer_config(comp, local_layer,
plane_state, NULL);
plane_state,cmdq_handle); plane_state->pending.async_config = false;@@ -444,6 +460,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) {
- struct cmdq_pkt *cmdq_handle; struct drm_crtc *crtc = &mtk_crtc->base; struct mtk_drm_private *priv = crtc->dev->dev_private; unsigned int pending_planes = 0, pending_async_planes = 0;
@@ -472,9 +489,18 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
if (priv->data->shadow_register) { mtk_disp_mutex_acquire(mtk_crtc->mutex);
mtk_crtc_ddp_config(crtc);
mtk_crtc_ddp_config(crtc, NULL);+#ifdef CONFIG_MTK_CMDQ
- if (mtk_crtc->cmdq_client) {
cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);mtk_crtc_ddp_config(crtc, cmdq_handle);cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);- }
+#endif mutex_unlock(&mtk_crtc->hw_lock); }
@@ -643,8 +669,8 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); struct mtk_drm_private *priv = crtc->dev->dev_private;
- if (!priv->data->shadow_register)
mtk_crtc_ddp_config(crtc);
if (!priv->data->shadow_register && !mtk_crtc->cmdq_client)
mtk_crtc_ddp_config(crtc, NULL);mtk_drm_finish_page_flip(mtk_crtc);
} @@ -787,5 +813,21 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, priv->num_pipes++; mutex_init(&mtk_crtc->hw_lock);
+#ifdef CONFIG_MTK_CMDQ
- mtk_crtc->cmdq_client =
cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base),2000);- if (IS_ERR(mtk_crtc->cmdq_client)) {
dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",drm_crtc_index(&mtk_crtc->base));mtk_crtc->cmdq_client = NULL;- }
- ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
drm_crtc_index(&mtk_crtc->base),&mtk_crtc->cmdq_event);- if (ret)
dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",drm_crtc_index(&mtk_crtc->base));+#endif return 0; }
Hi, Bibby:
I've tried to apply this series to 5.5-rc1, but there are many conflicts. Please resend this series based on 5.5-rc1.
And I've found that if I config CONFIG_MTK_CMDQ=m, the code inside '#ifdef CONFIG_MTK_CMDQ' would not be built. I think you should change this to '#if IS_ENABLED(CONFIG_MTK_CMDQ)'.
Regards, CK
On Thu, 2019-12-05 at 17:27 +0800, Bibby Hsieh wrote:
The CMDQ (Command Queue) in MT8183 is used to help update all relevant display controller registers with critical time limation. This patch add cmdq interface in ddp_comp interface, let all ddp_comp interface can support cpu/cmdq function at the same time.
These patches also can fixup cursor moving is not smooth when heavy load in webgl.
This patch depends on ptach: add drm support for MT8183 (https://patchwork.kernel.org/cover/11121519/) support gce on mt8183 platform (https://patchwork.kernel.org/cover/11255147) drm/mediatek: Refactor plane init/check and support rotation (https://pw-emeril.freedesktop.org/series/69015/) drm/mediatek: Check return value of mtk_drm_ddp_comp_for_plane (https://lore.kernel.org/patchwork/patch/1154517/)
Changes since v3:
- remove redundant code and variable
Changes since v2:
- move some changes to another patch
- disable layer in atomic_disable()
Changes since v1:
- remove redundant code
- merge the duplicate code
- use async instead of cursor
Changes since v0:
- remove redundant code
- remove patch "drm/mediatek: fix atomic_state reference counting" After remove this patch, the issue we met before is gone. So I do not add any extra code to do something.
Bibby Hsieh (7): drm/mediatek: use DRM core's atomic commit helper drm/mediatek: handle events when enabling/disabling crtc drm/mediatek: update cursors by using async atomic update drm/mediatek: disable all the planes in atomic_disable drm/mediatek: remove unused external function drm/mediatek: support CMDQ interface in ddp component drm/mediatek: apply CMDQ control flow
drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 67 ++++---- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 43 ++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 165 ++++++++++++++++---- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 + drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 132 ++++++++++++---- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 47 +++--- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 86 +--------- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 - drivers/gpu/drm/mediatek/mtk_drm_plane.c | 47 ++++++ drivers/gpu/drm/mediatek/mtk_drm_plane.h | 2 + 11 files changed, 381 insertions(+), 224 deletions(-)
dri-devel@lists.freedesktop.org
-
Bibby Hsieh -
CK Hu